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high performance, narrow-band transceiver ic ADF7021-V rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features high performance, low power, narrow-band transceiver enhanced performance adf7021-n with external vco frequency bands using external vco: 80 mhz to 960 mhz improved adjacent channel power (acp) and adjacent channel rejection (acr) compared with the adf7021-n programmable if filter bandwidths: 9 khz, 13.5 khz, and 18.5 khz modulation schemes: 2fsk, 3fsk, 4fsk, msk spectral shaping: gaussian and raised cosine filtering data rates: 0.05 kbps to 24 kbps power supply: 2.3 v to 3.6 v programmable output power: ?16 dbm to +13 dbm in 63 steps automatic power amplifier (pa) ramp control receiver sensitivity ?125 dbm at 250 bps, 2fsk ?122 dbm at 1 kbps, 2fsk patent pending, on-chip image rejection calibration on-chip fractional-n pll on-chip, 7-bit adc and temperature sensor fully automatic frequency control (afc) loop digital received signal strength indication (rssi) integrated tx/rx switch leakage current in power-down mode: 0.1 a applications narrow-band, short-range device (srd) standards etsi en 300 220 500 mw output power capabili ty in 869 mhz g3 subband with external pa high performance receiver rejection, blocking, and adjacent channel power (acp) fcc part 90 (meets emission mask d requirements) fcc part 95 arib std-t67 wireless metering narrow-band wireless telemetry functional block diagram 2fsk 3fsk 4fsk demodulator clock and data recovery 7-bit adc gain div r rfout lna pfd cp buffer osc1 osc2 n/n + 1 div p osc clkout test mux cpout ldo[1:4] muxout rset c r eg[1:4] ce ADF7021-V txrxclk swd txrxdata sle sdata sread sclk if filter pa ramp l2 mux 2fsk 3fsk 4fsk mod control gaussian/ raised cosine filter 3fsk encoding 1/2 2 0 8635-001 clk div - modulator serial port tx/rx control agc control afc control temp sensor rssi/ log amp r lna rfin rfin figure 1.
ADF7021-V rev. 0 | page 2 of 60 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? rf and pll specifications ........................................................... 4 ? transmission specifications ........................................................ 5 ? receiver specifications ................................................................ 6 ? digital specifications ................................................................... 9 ? general specifications ............................................................... 10 ? timing characteristics .............................................................. 10 ? timing diagrams ........................................................................ 11 ? absolute maximum ratings .......................................................... 14 ? esd caution ................................................................................ 14 ? pin configuration and function descriptions ........................... 15 ? typical performance characteristics ........................................... 17 ? frequency synthesizer ................................................................... 21 ? reference input ........................................................................... 21 ? muxout .................................................................................... 22 ? voltage controlled oscillator (vco) ...................................... 23 ? choosing a vco for best system performance ..................... 23 ? transmitter ...................................................................................... 24 ? rf output stage .......................................................................... 24 ? modulation schemes .................................................................. 24 ? spectral shaping ......................................................................... 26 ? modulation and filtering options ........................................... 27 ? transmit latency ........................................................................ 27 ? test pattern generator ............................................................... 27 ? receiver section .............................................................................. 28 ? rf front end ............................................................................... 28 ? if filter ......................................................................................... 28 ? rssi/agc .................................................................................... 28 ? demodulation, detection, and cdr ....................................... 30 ? receiver setup ............................................................................. 32 ? fsk demodulator optimization .............................................. 33 ? afc operation ........................................................................... 34 ? automatic sync word detection (swd) ................................ 35 ? applications information .............................................................. 36 ? if filter bandwidth calibration ............................................... 36 ? lna/pa matching ...................................................................... 37 ? image rejection calibration ..................................................... 38 ? packet structure and coding .................................................... 39 ? programming after initial power-up ..................................... 39 ? applications circuit ................................................................... 42 ? serial interface ................................................................................ 43 ? readback format ........................................................................ 43 ? interfacing to a microcontroller/dsp ..................................... 44 ? register 0n register ............................................................... 45 ? register 1oscillator register ................................................. 46 ? register 2transmit modulation register ............................ 47 ? register 3transmit/receive clock register ........................ 48 ? register 4demodulator setup register ............................... 49 ? register 5if filter setup register ......................................... 50 ? register 6if fine calibration setup register ..................... 51 ? register 7readback setup register ...................................... 52 ? register 8power-down test register .................................. 53 ? register 9agc register ......................................................... 54 ? register 10afc register ....................................................... 55 ? register 11sync word detect register ................................ 56 ? register 12swd/threshold setup register ........................ 56 ? register 133fsk/4fsk demodulation register ................. 57 ? register 14test dac register ............................................... 58 ? register 15test mode register ............................................. 59 ? outline dimensions ....................................................................... 60 ? ordering guide .......................................................................... 60 ? revision history 4/10revision 0: initial version
ADF7021-V rev. 0 | page 3 of 60 general description the ADF7021-V is a high performance, low power, narrow-band rf transceiver based on the adf7021-n . the architecture of the ADF7021-V transceiver is similar to that of the adf7021-n except that an external vco is used by the on-chip rf synthesizer for applications that require improved phase noise performance. the ADF7021-V is designed to operate in both the license-free ism bands and in the licensed bands from 80 mhz to 960 mhz. to minimize rf feedthrough and spurious emissions, the external vco operates at 2 or 4 the desired rf frequency; the ADF7021-V supports a maximum vco frequency operation of 1920 mhz. the 4 vco operation is programmable by enabling an additional on-chi p divide-by-2 outside the rf synthesizer loop and offers improved phase noise performance. as with the adf7021-n receiver, the if filter bandwidths of 9 khz, 13.5 khz, and 18.5 khz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications. the part has both gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. it is suitable for circuit applications targeted at the following: ? european etsi en 300 220 ? north american fcc part 15, part 90, and part 95 ? japanese arib std-t67 ? korean short-range device regulations ? chinese short-range device regulations a complete transceiver can be built using a small number of discrete external components, making the ADF7021-V very suitable for area-sensitive, high performance driven applications. the range of on-chip fsk modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. the ADF7021-V also supports protocols that dynamically switch among 2fsk, 3fsk, and 4fsk to maximize communication range and data throughput. the transmit section contains a low noise fractional-n pll with an output resolution of <1 ppm. the frequency-agile pll allows the ADF7021-V to be used in frequency-hopping spread spectrum (fhss) systems. the vco is external, which provides better phase noise and thus lower adjacent channel power (acp) and adjacent channel rejection (acr) compared with the adf7021-n . the vco tuning range extends from 0.2 v to 2 v, which should be taken into account when choosing the external vco. the transmitter output power is programmable in 63 steps from ?16 dbm to +13 dbm and has an automatic power amplifier ramp control to prevent spectral splatter and help meet regulatory standards. the transceiver rf frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. the device operates with a power supply range of 2.3 v to 3.6 v and can be powered down when not in use. a low if architecture is used in the receiver (100 khz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. the if filter has programmable bandwidths of 9 khz, 13.5 khz, and 18.5 khz. the ADF7021-V supports a wide variety of pro- grammable features, including rx linearity, sensitivity, and if bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. the receiver also features a patented automatic frequency control (afc) loop with programmable pull-in range that allows the pll to remove the frequency error in the incoming signal. the receiver achieves an image rejection performance of 50 db using a patent-pending ir calibration scheme that does not require the use of an external rf source. an on-chip adc provides readback of the integrated temper- ature sensor, external analog input, battery voltage, and rssi signal, which can eliminate the need for an external adc in some applications. the temperature sensor is accurate to 10c over the full operating temperature range of ?40c to +85c. this accuracy can be improved by performing a one-point cali- bration at room temperature and storing the result in memory.
ADF7021-V rev. 0 | page 4 of 60 specifications v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25c. all measurements are performed with the eval-ADF7021-Vdbxz using the pn9 data sequence, unless otherwise noted. the version number of etsi en 300 200-1 is v2.3.1. lbw = loop bandwidth and ifbw = if filter bandwidth. rf and pll specifications table 1. parameter min typ max unit test conditions/comments rf characteristics phase frequency detector (pfd) frequency rf/256 24 mhz maximum usable pfd at a particular rf frequency is limited by the minimum n divider value phase-locked loop (pll) normalized in-band phase noise floor 1 ?203 dbc/hz pll settling 155 s measured for a 100 khz frequency step to within 5 ppm accuracy, pfd = 19.68 mhz, lbw = 8 khz external vco tuning range 0.2 2 v pin l2 input sensitivity 0 dbm vco frequency < 1920 mhz reference input crystal reference 2 3.625 24 mhz external oscillator 2 , 3 3.625 24 mhz crystal start-up time 4 10 mhz xtal, 33 pf load capacitors, v dd = 3.0 v xtal bias = 20 a 0.930 ms xtal bias = 35 a 0.438 ms input level for external oscillator osc1 pin 0.8 v p-p clipped sine wave osc2 pin cmos levels v adc parameters v dd = 2.3 v to 3.6 v, t a = 25c integral nonlinearity (inl) 0.4 lsb differential nonlinearity (dnl) 0.4 lsb 1 this value can be used to calculate the in-band phase noise for any operating frequency. use the following equation to calculate the in-band phase noise performance as seen at the power amplifi er (pa) output: ?203 + 10 log( f pfd ) + 20 log n. 2 guaranteed by design. sample tested to ensure compliance. 3 a tcxo, vcxo, or ocxo can be used as an external oscillator. 4 crystal start-up time is the time from chip enable (ce) being asserted to correct clock frequency on the clkout pin.
ADF7021-V rev. 0 | page 5 of 60 transmission specifications lbw = loop bandwidth. table 2. parameter min typ max unit test conditions/comments data rate limited by the loop bandwidth 2fsk 0.05 18.5 kbps lbw must be 1.25 data rate for correct operation 3fsk 0.05 18.5 kbps lbw = 18.5 khz 4fsk 0.05 24 kbps lbw = 18.5 khz modulation frequency deviation (f dev ) 0.056 28.26 khz pfd = 3.625 mhz 0.306 156 khz pfd = 20 mhz frequency deviation resolution 56 hz pfd = 3.625 mhz gaussian filter bandwidth time (bt) 0.5 raised cosine filter alpha 0.5/0.7 programmable transmit power maximum transmit power 1 13 dbm v dd = 3.0 v, t a = 25c transmit power variation vs. temperature 1 db t a = ?40c to +85c transmit power variation vs. v dd 1 db v dd = 2.3 v to 3.6 v at 915 mhz, t a = 25c transmit power flatness 1 db 902 mhz to 928 mhz, v dd = 3 v, t a = 25c programmable step size 0.3125 db ?16 dbm to +13 dbm adjacent channel power (acp) gaussian 2fsk modulation, 13 dbm output power, pfd = 19.68 mhz, lbw = 6 khz 460 mhz 12.5 khz channel spacing ?47 dbm measured in a 8.5 khz bandwidth at 12.5 khz offset, 2.4 kbps pn9 data, f dev = 1.2 khz 25 khz channel spacing ?53 dbm measured in a 16 khz bandwidth at 25 khz offset, 4.8 kbps pn9 data, f dev = 2.4 khz 868 mhz compliant with etsi en 300 220 12.5 khz channel spacing ?44 dbm measured in a 8.5 khz bandwidth at 12.5 khz offset, 2.4 kbps pn9 data, f dev = 1.2 khz 25 khz channel spacing ?49 dbm measured in a 16 khz bandwidth at 25 khz offset, 4.8 kbps pn9 data, f dev = 2.4 khz modulation bandwidth 869.525 mhz, gaussian 2fsk modulation, 4.8 kbps, f dev = 2.4 khz, 10 dbm output power, 2 compliant with etsi en 300 220, lbw = 6 khz 125 khz offset ?74.5 dbm/1 khz 125 khz + 200 khz ?79 dbm/1 khz 125 khz + 400 khz ?69.5 dbm/10 khz 125 khz + 1 mhz ?62 dbm/ 100 khz emission mask fcc part 90 emission mask d, 100 hz resolution bandwidth, gaussian 2fsk modulation, lbw = 6 khz, 10 dbm output power, 2.4 kbps pn9 data, f dev = 1.2 khz 12.5 khz offset 460 mhz ?77 dbc occupied bandwidth 99.0% of total mean power, lbw = 6 khz, 10 dbm output power 2fsk, gaussian data filtering 12.5 khz channel spacing 4.0 khz 2.4 kbps pn9 data, f dev = 1.2 khz 25 khz channel spacing 8.5 khz 4.8 kbps pn9 data, f dev = 2.4 khz 2fsk, raised cosine data filtering 12.5 khz channel spacing 4.5 khz 2.4 kbps pn9 data, f dev = 1.2 khz 25 khz channel spacing 9.6 khz 4.8 kbps pn9 data, f dev = 2.4 khz
ADF7021-V rev. 0 | page 6 of 60 parameter min typ max unit test conditions/comments 3fsk, raised cosine filtering 12.5 khz channel spacing 4.3 khz 2.4 kbps pn9 data, f dev = 1.2 khz 25 khz channel spacing 8.5 khz 4.8 kbps pn9 data, f dev = 2.4 khz 4fsk, raised cosine filtering 25 khz channel spacing 11.3 khz 9.6 kbps pn9 data, f dev = 1.2 khz spurious emissions reference spurs ?65 dbc lbw = 8 khz harmonics 3 13 dbm output power second harmonic ?35/?52 dbc unfilt ered conductive/filtered conductive third harmonic ?43/?60 dbc unfilt ered conductive/filtered conductive all other harmonics ?36/?65 dbc unfiltered conductive/filtered conductive optimum pa load impedance f rf = 915 mhz 39 + j61 f rf = 868 mhz 48 + j54 f rf = 470 mhz 97.5 + j64.4 f rf = 450 mhz 98 + j65 f rf = 426 mhz 100 + j65 f rf = 315 mhz 129 + j63 f rf = 175 mhz 173 + j49 f rf = 169 mhz 74.5 + j48.5 1 measured as maximum unmodulated power. 2 suitable for etsi 500 mw tx requirements. 3 conductive filtered harmonic emissions measured on the eval-adf 7021-vdbxz, which includes a t-stage harmonic filter (two induc tors and one capacitor). receiver specifications lbw = loop bandwidth and ifbw = if filter bandwidth. table 3. parameter min typ max unit test conditions/comments data rate limited by the if filter bandwidth 1 2fsk 0.05 9.0 kbps ifbw = 9 khz 0.05 13.5 kbps ifbw = 13.5 khz 0.05 18.5 kbps ifbw = 18.5 khz 3fsk 0.05 18.5 kbps ifbw = 18.5 khz 4fsk 0.05 24 kbps ifbw = 18.5 khz sensitivity bit error rate (ber) = 10 ?3 2fsk sensitivity at 0.25 kbps ?125 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 1 kbps ?122 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 2.4 kbps ?119 dbm f dev = 1.2 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 4.8 kbps ?116 dbm f dev = 2.4 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 9.6 kbps ?114 dbm f dev = 4.8 khz, high sensitivity mode, ifbw = 18.5 khz gaussian 2fsk sensitivity at 0.25 kbps ?125 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 1 kbps ?122 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 2.4 kbps ?120 dbm f dev = 1.2 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 4.8 kbps ?117 dbm f dev = 2.4 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 9.6 kbps ?114 dbm f dev = 4.8 khz, high sensitivity mode, ifbw = 18.5 khz gmsk sensitivity at 4.8 kbps ?114.5 dbm f dev = 1.2 khz, high sensitivity mode, ifbw = 9.0 khz
ADF7021-V rev. 0 | page 7 of 60 parameter min typ max unit test conditions/comments raised cosine 2fsk sensitivity at 0.25 kbps ?125 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 1 kbps ?121 dbm f dev = 1 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 2.4 kbps ?120 dbm f dev = 1.2 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 4.8 kbps ?115 dbm f dev = 2.4 khz, high sensitivity mode, ifbw = 9.0 khz sensitivity at 9.6 kbps ?114 dbm f dev = 4.8 khz, high sensitivity mode, ifbw = 18.5 khz 3fsk sensitivity at 4.8 kbps ?110 dbm f dev = 2.4 khz, high sensitivity mode, ifbw = 18.5 khz, viterbi detection on raised cosine 3fsk sensitivity at 4.8 kbps ?110 dbm f dev = 2.4 khz, high sensitivity mode, ifbw = 13.5 khz, alpha = 0.5, viterbi detection on 4fsk sensitivity at 4.8 kbps ?112 dbm f dev (inner) 2 = 1.2 khz, high sensitivity mode, ifbw = 13.5 khz raised cosine 4fsk sensitivity at 4.8 kbps ?109 dbm f dev (inner) 2 = 1.2 khz, high sensitivity mode, ifbw = 13.5 khz, alpha = 0.5 input ip3 two-tone test, f lo = 860 mhz, f1 = f lo + 100 khz, f2 = f lo ? 800 khz low gain, enhanced linearity mode ?3 dbm lna_gain = 3, mixer_linearity = 1 medium gain mode ?13.5 dbm lna_gain = 10, mixer_linearity = 0 high sensitivity mode ?24 dbm lna_gain = 30, mixer_linearity = 0 adjacent channel rejection (acr) 868 mhz desired signal is 3 db above the sensitivity point of ?109.5 dbm as per en 300 220; rejection is measured as the level of an unmodulated interferer to cause a ber of 10 ?2 for the desired signal 12.5 khz channel spacing ?60 dbm ifbw = 9 khz, data rate = 0.25 kbps, f dev = 1 khz, lbw = 6 khz 25 khz channel spacing ?39 dbm ifbw = 9 khz, data rate = 0.25 kbps, f dev = 1 khz, lbw = 6 khz 12.5 khz channel spacing ?60 dbm ifbw = 9 khz, data rate = 1 kbps, f dev = 1 khz, lbw = 6 khz 25 khz channel spacing ?40 dbm ifbw = 9 khz, data rate = 1 kbps, f dev = 1 khz, lbw = 6 khz 12.5 khz channel spacing ?59.5 dbm ifbw = 9 khz, data rate = 2.4 kbps, f dev = 1.2 khz, lbw = 6 khz 25 khz channel spacing ?42 dbm ifbw = 9 khz, data rate = 2.4 kbps, f dev = 1.2 khz, lbw = 6 khz 12.5 khz channel spacing ?63 dbm ifbw = 9 khz, data rate = 4.8 kbps, f dev = 2.4 khz, lbw = 6 khz 25 khz channel spacing ?45 dbm ifbw = 9 khz, data rate = 4.8 kbps, f dev = 2.4 khz, lbw = 6 khz 25 khz channel spacing ?57 dbm ifbw = 18.5 khz, data rate = 9.6 kbps, f dev = 4.8 khz, lbw = 6 khz 460 mhz desired signal is at ?106.5 dbm; rejection is measured as the level of an unmodulated interferer to cause a ber of 10 ?2 for the desired signal 12.5 khz channel spacing ?59.5 dbm ifbw = 9 khz, data rate = 0.25 kbps, f dev = 1 khz, lbw = 6 khz 25 khz channel spacing ?37.5 dbm ifbw = 9 khz, data rate = 0.25 kbps, f dev = 1 khz, lbw = 6 khz 12.5 khz channel spacing ?60 dbm ifbw = 9 khz, data rate = 1 kbps, f dev = 1 khz, lbw = 6 khz 25 khz channel spacing ?41 dbm ifbw = 9 khz, data rate = 1 kbps, f dev = 1 khz, lbw = 6 khz 12.5 khz channel spacing ?62 dbm ifbw = 9 khz, data rate = 2.4 kbps, f dev = 1.2 khz, lbw = 6 khz 25 khz channel spacing ?43 dbm ifbw = 9 khz, data rate = 2.4 kbps, f dev = 1.2 khz, lbw = 6 khz 12.5 khz channel spacing ?61.5 dbm ifbw = 9 khz, data rate = 4.8 kbps, f dev = 2.4 khz, lbw = 6 khz 25 khz channel spacing ?44.5 dbm ifbw = 9 khz, data rate = 4.8 kbps, f dev = 2.4 khz, lbw = 6 khz 25 khz channel spacing ?56 dbm ifbw = 18.5 khz, data rate = 9.6 kbps, f dev = 4.8 khz, lbw = 6 khz cochannel rejection desired signal is 3 db above the sensitivity point of ?109.5 dbm; rejection is measured as the level of an interferer to cause a ber of 10 ?2 for the desired signal 868 mhz ?5 db ifbw = 9 khz, data rate = 4.8 kbps, f dev = 2.4 khz, lbw = 6 khz
ADF7021-V rev. 0 | page 8 of 60 parameter min typ max unit test conditions/comments image channel rejection desired signal (2fsk, 9.6 kbps, 4 khz deviation) is 3 db above the sensitivity point (ber = 10 ?2 ); modulated inter- ferer (2fsk, 9.6 kbps, 4 khz deviation) is placed at the image frequency of f rf ? 200 khz; the interferer level is increased until ber = 10 ?2 868 mhz 26/39 db uncalibrated/calibrated, 3 v dd = 3.0 v, t a = 25c 460 mhz 29/50 db uncalibrated/calibrated, 3 v dd = 3.0 v, t a = 25c blocking desired signal is 3 db above the sensitivity point of ?109.5 dbm; rejection is measured as the level of an unmodulated interferer to cause a ber of 10 ?2 for the desired signal; as per etsi en 300 220-1 1 mhz ?29.5 dbm 2 mhz ?26.5 dbm 5 mhz ?26 dbm 10 mhz ?25.5 dbm saturation (maximum input level) 12 dbm 2fsk mode, ber = 10 ?3 received signal strength indication (rssi) input power range 4 ?120 to ?47 dbm linearity 2 db input power range = ?100 dbm to ?47 dbm absolute accuracy 3 db input power range = ?100 dbm to ?47 dbm response time 333 s as per agc gain stage, agc clock = 3 khz automatic frequency loop (afc) pull-in range, minimum 0.5 khz range is programmable in register 10 (bits[db31:db24]) pull-in range, maximum 1.5 if_ filter_bw khz range is programmable in register 10 (bits[db31:db24]) response time 96 bits dependent on modulation index accuracy 0.5 khz input power range = ?100 dbm to +12 dbm rx spurious emissions 5 external 920 mhz vco ?54/?88 dbm <1 ghz at antenna input, unfiltered conductive/filtered conductive external 920 mhz vco ?45/?66 dbm >1 ghz at antenna input, unfiltered conductive/filtered conductive external 1738 mhz vco ?85/?85 dbm <1 ghz at antenna input, unfiltered conductive/filtered conductive external 1738 mhz vco ?39/?52 dbm >1 ghz at antenna input, unfiltered conductive/filtered conductive lna input impedance rfin to rfgnd; refer to the an-859 application note for other frequencies f rf = 915 mhz 24 ? j60 f rf = 868 mhz 26 ? j63 f rf = 470 mhz 58 ? j124 f rf = 450 mhz 63 ? j129 f rf = 426 mhz 68 ? j134 f rf = 315 mhz 96 ? j160 f rf = 175 mhz 178 ? j190 f rf = 169 mhz 182.5 ? j194 1 using gaussian or raised cosine filtering. the frequency deviation should be chosen to ensure that the transmit-occupied signa l bandwidth is within the receiver if filter bandwidth. 2 4fsk f dev is defined as the frequency spacing from the rf carrier to +f dev or ?f dev . it is also equal to half the frequency spacing between adjacent symbols. 3 calibration of the image rejectio n used an external rf source. 4 for received signal levels < ?100 dbm, it is recommended that the rssi readback value be averaged over a number of samples to improve rssi accuracy at low input power. 5 filtered conductive receive sp urious emissions are meas ured on the eval-ADF7021-Vdbxz, which includes a t-stag e harmonic filte r (two inductors and one capacitor).
ADF7021-V rev. 0 | page 9 of 60 digital specifications table 4. parameter min typ max unit test conditions/comments timing information chip enabled to regulator ready 50 s creg[1:4] = 100 nf chip enabled to tx mode 32-bit register write time = 50 s tcxo reference 1 ms depends on vco settling xtal 2 ms depends on vco settling chip enabled to rx mode 32-bit register write time = 50 s, if filter coarse calibration only tcxo reference 1.2 ms depends on vco settling xtal 2.2 ms depends on vco settling tx-to-rx turnaround time agc settling + (5 t bit ) ms time to synchronized data output; includes agc settling (three agc levels ) and cdr synchronization; t bit = data bit period; afc settling not included logic inputs input high voltage, v inh 0.7 v dd v input low voltage, v inl 0.2 v dd v input current, i inh /i inl 1 a input capacitance, c in 10 pf control clock input 50 mhz logic outputs output high voltage, v oh vdd2 ? 0.4 v i oh = 500 a output low voltage, v ol 0.4 v i ol = 500 a clkout rise/fall time 5 ns clkout load 10 pf
ADF7021-V rev. 0 | page 10 of 60 general specifications table 5. parameter min typ max unit test conditions/comments temperature range (t a ) ?40 +85 c power supplies voltage supply, v dd 2.3 3.6 v all vddx pins must be tied together transmit current consumption 1 , 2 v dd = 3.0 v, pa is matched into 50 868 mhz 0 dbm 17.6 ma 5 dbm 20.8 ma 10 dbm 27.1 ma 460 mhz 0 dbm 13.8 ma 5 dbm 17 ma 10 dbm 23 ma receive current consumption 2 v dd = 3.0 v 868 mhz low current mode 19.3 ma high sensitivity mode 21.7 ma 460 mhz low current mode 16.3 ma high sensitivity mode 18.3 ma power-down current consumption 2 low power sleep mode 0.1 1 a ce low 1 the transmit current consumption tests used the same co mbined pa and lna match ing network as that used on the eval-ADF7021-Vdb xz evaluation boards. improved pa efficiency is achieved by using a separate pa matching network. 2 device current only. vco and tcxo currents are excluded. timing characteristics v dd = 3 v 10%, gnd = 0 v, t a = 25c, unless otherwise noted. guaranteed by design but not production tested. table 6. parameter limit at t min to t max unit description t 1 >10 ns sdata to sclk setup time t 2 >10 ns sdata to sclk hold time t 3 >25 ns sclk high duration t 4 >25 ns sclk low duration t 5 >10 ns sclk to sle setup time t 6 >20 ns sle pulse width t 8 <25 ns sclk to sread data valid, readback t 9 <25 ns sread hold time after sclk, readback t 10 >10 ns sclk to sle disable time, readback t 11 5 < t 11 < (? t bit ) ns txrxclk negative edge to sle t 12 >5 ns txrxdata to txrxclk setup time (tx mode) t 13 >5 ns txrxclk to txrxdata hold time (tx mode) t 14 5 < t 14 < (? t bit ) s txrxclk negative edge to sle t 15 >? t bit s sle positive edge to positive edge of txrxclk (rx mode)
ADF7021-V rev. 0 | page 11 of 60 timing diagrams serial interface sclk sle db31 (msb) db30 db1 (control bit c2) db2 (control bit c3) s data db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 t 5 08635-002 figure 2. serial interface timing diagram t 8 t 3 t 1 t 2 t 10 t 9 xr v 1 6 rv15 rv2 sclk sdata sle sread reg 7 db0 (control bit c1) rv1 x 08635-003 figure 3. serial interface readback timing diagram 2fsk/3fsk timing txrxclk data t xrxdata 1 data rate/32 1/data rate 08635-004 figure 4. txrxdata/txrxclk ti ming diagram in receive mode txrxclk data txrxdata sample fetch 1/data rate 08635-005 figure 5. txrxdata/txrxclk timi ng diagram in transmit mode
ADF7021-V rev. 0 | page 12 of 60 4fsk timing in 4fsk receive mode, msb/lsb synchronization should be guaranteed by detection of the swd pin in the receive bit stream. rx symbol msb rx symbol lsb rx symbol msb rx symbol lsb tx symbol msb tx symbol lsb txrxdata txrxclk sle rx mode tx mode register 0 write switch from rx to tx tx/rx mode tx symbol msb t 11 t 12 t 13 t bit t symbol 08635-006 figure 6. receive-to-transmit timing diagram in 4fsk mode tx symbol msb tx symbol lsb tx symbol msb tx symbol lsb rx symbol lsb rx symbol msb txrxdata txrxclk sle tx mode rx mode register 0 write switch from tx to rx tx/rx mode t 15 t 14 t bit t symbol 08635-007 figure 7. transmit-to-receive timing diagram in 4fsk mode
ADF7021-V rev. 0 | page 13 of 60 uart/spi mode uart mode is enabled by setting register 0, bit db28 to 1. spi mode is enabled by setting register 0, bit db28 to 1 and setting register 15, bits[db19:db17] to 0x7. the transmit/receive data clock is available on the clkout pin. tx bit tx bit tx bit tx bit txrxclk (transmit data input in uart/spi mode.) clkout (transmit/receive data clock in spi mode. not used in uart mode.) tx mode tx/rx mode txrxdata (receive data output in uart/spi mode.) high-z tx bit t bit fetch sample 0 8635-008 figure 8. transmit timing diagram in uart/spi mode rx bit rx bit rx bit rx bit txrxclk (transmit data input in uart/spi mode.) clkout (transmit/receive dat a clock in spi mode. not used in uart mode.) rx mode tx/rx mode txrxdata (receive data output in uart/spi mode.) high-z rx bit t bit fetch sample 0 8635-009 figure 9. receive timing diagram in uart/spi mode
ADF7021-V rev. 0 | page 14 of 60 absolute maximum ratings t a = 25c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. parameter rating v dd to gnd 1 ?0.3 v to +5 v analog i/o voltage to gnd 1 ?0.3 v to vddx + 0.3 v digital i/o voltage to gnd 1 ?0.3 v to vddx + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c mlf ja thermal impedance 26c/w reflow soldering peak temperature 260c time at peak temperature 40 sec this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution 1 gnd = gnd1 = gnd2 = gnd4 = rfgnd = 0 v.
ADF7021-V rev. 0 | page 15 of 60 pin configuration and fu nction descriptions 08635-011 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 vcoin creg1 vdd1 rfout rfgnd rfin rfin r lna vdd4 rset creg4 gnd4 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce clkout txrxdata txrxclk swd vdd2 creg2 adcin notes 1. the exposed paddle must be connected to the ground plane. gnd2 sclk sread sdata sle cvco gnd1 l1 gnd l2 vdd cpout creg3 vdd3 osc1 osc2 muxout 1 2 3 4 5 6 7 8 9 10 11 12 pin 1 indicator ADF7021-V top view (not to scale) figure 10. pin configuration table 8. pin function descriptions pin no. mnemonic description 1 vcoin do not connect. 2 creg1 regulator voltage for pa block. place a series 3.9 resistor and a 100 nf capacitor between this pin and ground for regulator stability and noise rejection. 3 vdd1 voltage supply for pa block. place de coupling capacitors of 0.1 f and 100 pf as close as possible to this pin. tie all vddx pins together. 4 rfout the modulated signal is available at this pin. o utput power levels are from ?16 dbm to +13 dbm. the output should be impedance matched to the desired load using suitable components. 5 rfgnd ground for output stage of transmitter. tie all gnd pins together. 6 rfin lna input for receiver section. input matching is re quired between the antenna and the differential lna input to ensure maximum power transfer. 7 rfin complementary lna input. 8 r lna external bias resistor for lna. optimum resistor is 1.1 k with 5% tolerance. 9 vdd4 voltage supply for lna/mixer block. decouple this pin to ground with a 10 nf capacitor. tie all vddx pins together. 10 rset external resistor. sets charge pump current and some internal bias currents. use a 3.6 k resistor with 5% tolerance. 11 creg4 regulator voltage for lna/mixer block. place a 100 nf capacitor between this pin and ground for regulator stability and noise rejection. 12, 19, 22 gnd4 ground for lna/mixe r block. tie all gnd pins together. 13 to 16 mix_i, mix_i , mix_q, mix_q signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 17, 18, 20, 21 filt_i, filt_i , filt_q, filt_q , signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 23 test_a signal chain test pin. this pin is high impedance under normal conditions and should be left unconnected. 24 ce chip enable. bringing ce low puts the ADF7021-V into complete power-down. register values are lost when ce is low, and the part must be reprogrammed after ce is brought high. 25 sle load enable, cmos input. when sle goes high, the data stored in the shift registers is loaded into one of the 16 latches. a latch is selected using the control bits. 26 sdata serial data input. the serial data is loaded msb first with the four lsbs as the control bits. this pin is a high impedance cmos input.
ADF7021-V rev. 0 | page 16 of 60 pin no. mnemonic description 27 sread serial data output. this pin is used to feed readba ck data from the ADF7021-V to the microcontroller. the sclk input is used to clock each readback bit (f or example, afc or adc) from the sread pin. 28 sclk serial clock input. the serial clock is used to clock in the serial data to the registers. the data is latched into the 32-bit shift register on the sclk risi ng edge. this pin is a digital cmos input. 29 gnd2 ground for digital block. tie all gnd pins together. 30 adcin analog-to-digital converter input. the internal 7-bit adc can be accessed through this pin. full scale is 0 v to 1.9 v. readback is through the sread pin. 31 creg2 regulator voltage for digital block. place a 100 nf ca pacitor between this pin and ground for regulator stability and noise rejection. 32 vdd2 voltage supply for digital block. place a decoupling capa citor of 10 nf as close as possible to this pin. tie all vddx pins together. 33 swd sync word detect. the ADF7021-V asserts this pin when it finds a match for the sync word sequence. this provides an interrupt for an external microcontroller, indicating that valid data is being received. 34 txrxdata transmit data input/received data ou tput. this is a digital pin, and norm al cmos levels apply. in uart/spi receive mode, this pin provides an output for the rece ived data. in uart/spi transmit mode, this pin is high impedance. 35 txrxclk outputs the data clock in both receive and transmit mode s. this is a digital pin, and normal cmos levels apply. the positive clock edge is matched to the cent er of the received data. in standard transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. in uart/spi transmit mo de, this pin is used to in put the transmit data. in uart/spi receive mode, this pin is high impedance. 36 clkout divided-down version of the crystal reference with output driver. the digital clock output can be used to drive several other cmos inputs, such as a microcontroller clock. the output has a 50:50 mark/space ratio and is inverted with respect to the reference. pl ace a series 1 k resistor as close as possible to the pin in applications where the clkout feature is used. 37 muxout provides the digital_lock_detect signal. this signal is used to determine whether the pll is locked to the correct frequency. it also provides other signals such as regulator_ready, which is an indicator of the status of the serial interface regulator. 38 osc2 connect the reference crystal between this pin and osc1. a tcxo reference can be used by driving this pin with cmos levels and disabling the internal crystal oscillator. 39 osc1 connect the reference crystal between this pin and osc2. a tcxo reference can be used by driving this pin with ac-coupled 0.8 v p-p levels and by enabling the internal crystal oscillator. 40 vdd3 voltage supply for charge pump and pll dividers. decoup le this pin to ground with a 10 nf capacitor. tie all vddx pins together. 41 creg3 regulator voltage for charge pump and pll dividers. place a 100 nf capacitor between this pin and ground for regulator stability and noise rejection. 42 cpout charge pump output. this output generates current pu lses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 43 vdd voltage supply for rf circuitry. place a decoupling capacitor of 10 nf as close as possible to this pin. tie all vddx pins together. 44 l2 vco buffer input. 45 gnd ground. tie all gnd pins together. 46 l1 do not connect. 47 gnd1 ground. tie all gnd pins together. 48 cvco do not connect. ep exposed paddle the exposed paddle must be connected to the ground plane.
ADF7021-V rev. 0 | page 17 of 60 typical performance characteristics ? 80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1 10 100 1k 10k 100k frequency offset (khz) phase noise (dbc/hz) 08635-077 rf freq = 460mhz tcxo = 19.2mhz i cp = 0.3ma i cp = 0.9ma figure 11. phase noise response at 460 mhz, v dd = 3 v ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1 10 100 1k 10k frequency offset (khz) phase noise (dbc/hz) 08635-078 i cp = 0.3ma i cp = 0.9ma i cp = 1.5ma i cp = 2.1ma rf freq = 868mhz tcxo = 19.2mhz figure 12. phase noise response at 868 mhz, v dd = 2.3 v 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?25,000 ?20,000 ?15,000 ?10,000 ?5000 0 5000 10,000 15,000 20,000 25,000 frequency offset from carrier (hz) output power (dbm) 08635-079 fcc part 90 emission mask d demodulation = gfsk data rate = 2.4kbps f dev = 1.2khz rf freq = 470mhz ifbw = 4khz figure 13. output spectrum in fcc part 90 emission mask d and gfsk modes ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 pa setting rf output power (dbm) pa_bias = 5a pa_bias = 11a pa_bias = 9a pa_bias = 7a 08635-012 figure 14. rf output power vs. pa setting 20 0 ?20 ?40 ?60 ?80 ?100 300 800 1300 1800 2300 2800 frequency (mhz) output power (dbm) 08635-013 figure 15. pa output harmonic response with t-stage lc filter 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 867.97 867.98 867.99 868.00 868.01 868.02 868.03 frequency (mhz) output power (dbm) 08635-014 2fsk gfsk data rate = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 868mhz figure 16. output spectrum in 2fsk and gfsk modes
ADF7021-V rev. 0 | page 18 of 60 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 867.97 867.98 867.99 868.00 868.01 868.02 868.03 frequency (mhz) output power (dbm) 08635-015 2fsk rc2fsk data rate = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 868mhz figure 17. output spectrum in 2fsk and raised cosine 2fsk modes 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 867.97 867.98 867.99 868.00 868.01 868.02 868.03 frequency (mhz) output power (dbm) 08635-016 3fsk rc3fsk data rate = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 868mhz figure 18. output spectrum in 3fsk and raised cosine 3fsk modes 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 867.94 867.96 867.98 868.00 868.02 868.04 868.06 frequency (mhz) output power (dbm) 08635-017 4fsk rc4fsk data rate = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 868mhz figure 19. output spectrum in 4fsk and raised cosine 4fsk modes frequency offset (khz) output power (dbm) 0 ?10 10 ?20 ?30 ?40 ?100 ?50 50 0 100 ?50 ?60 ramp rate: cw only 256 codes/bit 128 codes/bit 64 codes/bit 32 codes/bit trace = max hold pa on/off rate = 3hz pa on/off cycles = 10,000 v dd = 3.0v 08635-018 figure 20. output spect rum in maximum hold for various pa ramp rate options 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?125 ?123 ?121 ?119 ?117 ?115 ?113 ?111 ?109 ?107 ?105 rf input power (dbm) log be r 08635-019 data rate = 2.4kbps f dev = 4.8hz rf freq = 868mhz ifbw = 9khz ?40c, 2.3v ?40c, 3v ?40c, 3.6v +25c, 2.3v +25c, 3v +25c, 3.6v +85c, 2.3v +85c, 3v +85c, 3.6v figure 21. 2fsk sensitivity vs. v dd and temperature at 868 mhz 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?127 ?125 ?123 ?121 ?119 ?117 ?115 ?113 ?111 rf input power (dbm) log be r 08635-020 data rate = 1.2kbps f dev = 2.4hz rf freq = 460mhz ifbw = 9khz ?40c, 2.3v ?40c, 3v ?40c, 3.6v +25c, 2.3v +25c, 3v +25c, 3.6v +85c, 2.3v +85c, 3v +85c, 3.6v figure 22. 2fsk sensitivity vs. v dd and temperature at 460 mhz
ADF7021-V rev. 0 | page 19 of 60 0.6 0.5 0.4 0.3 0.2 0.1 0 ?130 ?125 ?120 ?115 ?110 ?105 rf input power (dbm) bit error rate 08635-021 ?40c, 2.3v ?40c, 3v ?40c, 3.6v +25c, 2.3v +25c, 3v +25c, 3.6v +85c, 2.3v +85c, 3v +85c, 3.6v data rate = 1.2kbps f dev = 2.4hz rf freq = 868mhz ifbw = 9khz figure 23. 2fsk sensitivity vs. v dd and temperature at 868 mhz 0.6 0.5 0.4 0.3 0.2 0.1 0 ?130 ?125 ?120 ?115 ?110 ?105 rf input power (dbm) bit error rate 08635-022 ?40c, 2.3v ?40c, 3v ?40c, 3.6v +25c, 2.3v +25c, 3v +25c, 3.6v +85c, 2.3v +85c, 3v +85c, 3.6v data rate = 1.2kbps f dev = 2.4hz rf freq = 460mhz ifbw = 9khz figure 24. 2fsk sensitivity vs. v dd and temperature at 460 mhz 90 100 70 50 30 10 80 60 40 20 0 ?10 ?20 ?15 ?10 ?5 0 5 10 15 20 frequency offset (mhz) blocking (db) 08635-024 figure 25. wideband interference reject ion (modulated carrier is swept 20 mhz either side of an 868 mhz modulated gfsk 2.4 khz/4.8 kbps wanted signal at the sensitivity point (?106.5 dbm); the power level of the blocker is adjusted to give a ber of 10 ?2 ; interferer is a gfsk prbs15 4.8 khz/2.4 khz signal) ?140 ?120 ?100 ?80 ?60 ?40 ? 20 ?122.5 ?112.5 ?102.5 ?92.5 ?82.5 ?72.5 ?62.5 ?52.5 ?42.5 actual rf input level rf input power (dbm) rssi level (dbm) rssi readback level 08635-023 figure 26. digital rssi readback linearity 80 70 60 50 40 30 20 10 0 ?10 459.75 459.70 459.80 459.85 459.90 459.95 460.00 460.05 460.10 460.15 blocker frequency (mhz) blocking (db) 08635-080 calibrated uncalibrated figure 27. image rejection, uncalibrated vs. calibrated 08635-025 2.5 0 ?2.5 ?5.0 ?7.5 ?10.0 ?12.5 ?15.0 ?17.5 ?20.0 ?22.5 ?25.0 ?27.5 ?30.0 ?32.5 ?35.0 ?37.5 90 92 94 96 98 100 102 104 106 108 110 attenuation (db) if frequency (khz) ?40c +90c figure 28. variation of if filter response with temperature (if_filter_bw = 9 khz, temperature range is ?40c to +90c in 10 steps)
ADF7021-V rev. 0 | page 20 of 60 lna gain, filter gain sensitivity (dbm) ?130 ?120 ?110 ?100 ?90 ?80 ? 70 3, 72 (low gain mode) 10, 72 (medium gain mode) 30, 72 (high gain mode) high mixer linearity default mixer linearity 2fsk modulation data rate = 9.6kbps f dev = 4khz ifbw = 12.5khz demod = correlator sensitivity @ ber = 10 ?3 ip3 = ?3dbm ip3 = ?5dbm ip3 = ?9dbm ip3 = ?13.5dbm ip3 = ?24dbm ip3 = ?20dbm 08635-028 modulation index sensitivity point (dbm) ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ? 100 0 0.2 0.4 0.6 0.8 1.0 1.2 rf freq = 860mhz 2fsk modulation data rate = 9.6kbps ifbw = 25khz v dd = 3.0v temperature = 25c discriminator bandwidth = 1 fsk frequency deviation discriminator bandwidth = 2 fsk frequency deviation 08635-026 figure 31. 2fsk receiver sensitivity vs. lna gain/if filter gain and mixer linearity settings (input ip3 at each setting also shown) figure 29. 2fsk sensitivity vs. modulation index and correlator discriminator bandwidth ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ?100 3fsk modulation v dd = 3.0v, temp = 25c data rate = 9.6kbps f dev = 2.4khz rf freq = 868mhz ifbw = 18.75khz input power (dbm) log ber ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 viterbi detection threshold detection 08635-027 figure 30. 3fsk receiver sensitivity using viterbi detection and threshold detection
ADF7021-V rev. 0 | page 21 of 60 frequency synthesizer reference input the on-board crystal oscillator circuitry (see figure 32 ) can use a quartz crystal as the pll reference. a quartz crystal with a fre- quency tolerance of 10 ppm for narrow-band applications is recommended. it is possible to use a quartz crystal with >10 ppm tolerance, but compensation for the frequency error of the crystal is necessary to comply with the absolute frequency error speci- fications of narrow-band regulations (for example, arib std-t67 and etsi en 300 220). the oscillator circuit is enabled by setting bit db12 in register 1 high. it is enabled by default on power-up and is disabled by bringing ce low. errors in the crystal can be corrected using the automatic frequency control (afc) feature or by adjusting the fractional-n value (see the n counter section). osc1 cp1 cp2 osc2 08635-030 figure 32. crystal oscillator circuit on the ADF7021-V two parallel resonant capacitors are required for oscillation at the correct frequency. their values are dependent on the crystal specification. the resonant capacitors should be selected to ensure that the series value of capacitance added to the pcb track capacitance adds up to the specified load capacitance of the crystal, usually 12 pf to 20 pf. track capacitance values vary from 2 pf to 5 pf, depending on board layout. when possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. using a tcxo reference a single-ended reference (tcxo, vcxo, or ocxo) can also be used with the ADF7021-V. this is recommended for applications that have absolute frequency accuracy requirements of <10 ppm, such as applications requiring compliance with arib std-t67 or etsi en 300 220. the following are two options for inter- facing the ADF7021-V to an external reference oscillator. ? an oscillator with cmos output levels can be applied to osc2. the internal oscillator circuit should be disabled by setting bit db12 in register 1 low. ? an oscillator with 0.8 v p-p levels can be ac-coupled through a 22 pf capacitor into osc1. the internal oscillator circuit should be enabled by setting bit db12 in register 1 high. programmable crystal bias current bias current in the oscillator circuit can be configured from 20 a to 35 a by writing to the xtal_bias bits (register 1, bits[db14:db13]). increasing the bias current allows the crystal oscillator to power up faster. clkout divider and buffer the clkout circuit takes the reference clock signal from the oscillator section, shown in figure 32 , and supplies a divided- down, 50:50 mark/space signal to the clkout pin. the clkout signal is inverted with respect to the reference clock. an even divide from 2 to 30 is available; this divide number is set in register 1, bits[db10:db7]. on power-up, the clkout defaults to divide-by-8. v dd clkout enable bit clkout osc1 divider 1to 15 2 08635-031 figure 33. clkout stage to disable clkout, set the divide number to 0. the output buffer can drive a load of up to 20 pf with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a series resistor (1 k) can be used to slow the clock edges to reduce these spurs at the clkout frequency. r counter the 3-bit r counter divides the reference input frequency by an integer from 1 to 7. the divided-down signal is presented as the reference clock to the phase frequency detector (pfd). the divide ratio is set in register 1, bits[db6:db4]. maximizing the pfd frequency reduces the n value. this reduces the noise multi- plied at a rate of 20 log(n) to the output and reduces occurrences of spurious components. register 1 defaults to r = 1 on power-up. pfd (hz) = xtal / r loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 34 . charge pump out vco 08635-032 figure 34. typical loop filter configuration the loop should be designed so that the loop bandwidth (lbw) is approximately 6 khz. this provides a good compromise between in-band phase noise and out-of-band spurious rejection. widening the lbw excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. the loop filter design on the eval-ADF7021-Vdbxz should be used for optimum performance.
ADF7021-V rev. 0 | page 22 of 60 the free design tool adi simsrd? design studio can also be used to design loop filters for the ADF7021-V. see the adisimsrd design studio website ( www.analog.com/adisimsrd ) for details). n counter the feedback divider in the ADF7021-V pll consists of an 8-bit integer counter (set using register 0, bits[db26:db19]) and a 15-bit, - fractional-n divider (set using register 0, bits[db18:db4]). the integer counter is the standard pulse- swallow type that is common in plls. it sets the minimum integer divide value to 23. the fractional divide value provides very fine resolution at the output, where the output frequency of the pll is calculated as ? ? ? ? ? ? ? ? + = 15 2 _ _ n fractional n integer r xtal f out when rf_divide_by_2 is enabled (see the voltage controlled oscillator (vco) section), this formula becomes ? ? ? ? ? ? + = 15 2 _ 0.5 n fractional integer_n r xtal f out the combination of integer_n (maximum = 255) and fractional_n (maximum = 32,768/32,768) gives a maximum n divider of 255 + 1. therefore, the minimum usable pfd is () 1255 (hz) + = frequency output required maximum pfd min for example, when operating in the european 868 mhz to 870 mhz band, pfd min = 3.4 mhz. vco n third-order - ? modulator pfd/ charge pump r integer_n fractional_n reference in 08635-033 figure 35. fractional-n pll voltage regulators the ADF7021-V contains four regulators to supply stable voltages to the part. the nominal regulator voltage is 2.3 v. regulator 1 requires a 3.9 resistor and a 100 nf capacitor in series between creg1 and ground, whereas the other regula- tors require a 100 nf capacitor connected between cregx and ground. when ce is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 ma. bringing the ce pin low disables the regulators, reduces the supply current to less than 1 a, and erases all values held in the registers. the serial interface operates from a regulator supply. therefore, to write to the part, ce must be high and the regulator voltage must be stabilized. regulator status (creg4) can be monitored using the regulator_ready signal from the muxout pin. muxout the muxout pin allows access to various digital points in the ADF7021-V. the state of muxout is controlled in register 0, bits[db31:db29]. regulator_ready regulator_ready is the default setting on muxout after the transceiver is powered up. the power-up time of the regulator is typically 50 s. because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7021-V can be programmed. the regulator status can be monitored at muxout. when the regulator ready signal on muxout is high, programming of the ADF7021-V can begin. regulator_ready (default) digital_lock_detect rssi_ready tx_rx logic_zero tristate mux control gnd v dd muxout filter_cal_complete logic_one 08635-034 figure 36. muxout circuit filter_cal_complete muxout can be set to filter_cal_complete. this signal goes low for the duration of both a coarse if filter calibration and a fine if filter calibration. it can be used as an interrupt to a microcontroller to signal the end of the if filter calibration. digital_lock_detect digital_lock_detect indicates when the pll has locked. the lock detect circuit is located at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until a 25 ns phase error is detected at the pfd. rssi_ready muxout can be set to rssi_ready. this indicates that the internal analog rssi has settled and that a digital rssi readback can be performed. tx_rx tx_rx signifies whether the ADF7021-V is in transmit or receive mode. when in transmit mode, this signal is low. when in receive mode, this signal is high. it can be used to control an external tx/rx switch.
ADF7021-V rev. 0 | page 23 of 60 the vco tuning voltage can be checked for a particular rf output frequency by measuring the voltage on the cpout pin when the part is fully powered up in transmit or receive mode. the vco tuning range of the external vco must be 0.2 v to 2 v. voltage controlled oscillator (vco) to minimize feedthrough and spurious emissions, the external vco must be chosen to operate at a minimum of twice the required rf frequency. the vco frequency is divided by 2 inside the synthesizer loop, providing the required frequency for the transmitter and for the local oscillator (lo) of the receiver. for improved phase noise performance, an additional divide-by-2 can be enabled by setting the rf_divide_by_2 bit (bit db18) in register 1. the input impedance of the l2 pin is programmable and can be selected to have a high impedance value or 50 impedance, depending on the vco selected. the impedance of this pin can be set using the buffer_impedance bit (bit db17) in register 1. choosing a vco for best system performance as an example, for 80 mhz operation, a 160 mhz external vco could be used with the rf_divide_by_2 bit disabled, or a 320 mhz vco could be used with the rf_divide_by_2 bit enabled to support operation in the 80 mhz band. assuming that both vcos have similar phase noise performance, the 320 mhz design using the additional divide-by-2 should result in improved transmit acp, as well as improved acr, blocking, and image rejection in the receiver. the interaction between the rf vco frequency and the refer- ence frequency can lead to fractional spur creation. when the synthesizer is in fractional mode (that is, the rf vco and reference frequencies are not integer related), spurs can appear on the vco output spectrum at an offset frequency that corresponds to the difference frequency between an integer multiple of the reference and the vco frequency. the maximum vco frequency of operation supported on the ADF7021-V is 1920 mhz, which results in a maximum rf channel frequency of 960 mhz using a 2 vco or 480 mhz using a 4 vco. these spurs are attenuated by the loop filter. they are more noticeable on channels close to integer multiples of the reference where the difference frequency may be inside the loop bandwidth (thus, the name integer boundary spurs). the occurrence of these spurs is rare because the integer frequencies are around multiples of the reference, which is typically >10 mhz. to avoid having very small or very large values in the fractional register, choose a suitable reference frequency. vco 2 n r 2 pfd/cp ADF7021-V external components 08635-036 mux to pa loop filter ref tcxo/xtal synth frequency in addition to spurious considerations, the selection of a high performance vco with very low phase noise is essential to minimize the acp performance of the transmitter and to maximize the acr and blocking resilience of the receiver. figure 37. voltage controlled oscillator (vco)
ADF7021-V rev. 0 | page 24 of 60 transmitter rf output stage the power amplifier (pa) of the ADF7021-V is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dbm into a 50 load at a maximum frequency of 960 mhz. the pa output current and, consequently, the output power are programmable over a wide range. the pa configuration is shown in figure 38 . the output power is set using register 2, bits[db18:db13]. idac 2 6 register 2, bits[db18:db13] register 2, bit db7 register 2, bits[db12:db11] + rfgnd rfout from vco register 0, bit db27 08635-037 figure 38. pa configuration the pa is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. depending on the applica- tion, users can design a matching network for the pa to exhibit optimum efficiency at the desired radiated output power level for a wide range of antennas, such as loop or monopole antennas. see the lna/pa matching section for more information. pa ramping when the pa is switched on or off quickly, its changing input impedance momentarily disturbs the vco output frequency. this process is called vco pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier frequency. some radio emissions regulations place limits on these pa transient-induced spurs (for example, the etsi en 300 220 regulations). by gradually ramping the pa on and off, pa transient spurs are minimized. the ADF7021-V has built-in pa ramping configurability. as figure 39 illustrates, there are eight ramp rate settings, defined as a certain number of pa setting codes per one data bit period. the pa steps through each of its 64 code levels but at different speeds for each setting. the ramp rate is set by configuring bits[db10:db8] in register 2. if the pa is enabled/disabled by the pa_enable bit (register 2, bit db7), it ramps up and down. if it is enabled/disabled by the tx/rx bit (register 0, bit db27), it ramps up and turns hard off. data bits pa ramp 0 (no ramp) pa ramp 1 (256 codes per bit) pa ramp 2 (128 codes per bit) pa ramp 3 (64 codes per bit) pa ramp 4 (32 codes per bit) pa ramp 5 (16 codes per bit) pa ramp 6 (8 codes per bit) pa ramp 7 (4 codes per bit) 1 2 3 4 ... 8 ... 1 6 08635-038 figure 39. pa ramping settings pa bias currents the pa_bias bits (register 2, bits[db12:db11]) facilitate an adjustment of the pa bias current to further extend the output power control range, if necessary. if this feature is not required, the default value of 9 a is recommended. if output power greater than 10 dbm is required, a pa bias setting of 11 a is recommended. the output stage is powered down by resetting register 2, bit db7 to 0. modulation schemes the ADF7021-V supports 2fsk, 3fsk, and 4fsk modulation. the implementation of these modulation schemes is shown in figure 40 . vco n third-order - modulator pfd/ charge pump ref integer_n tx_frequency_ deviation to pa stage 1 ? d 2 pr shaping 4fsk bit symbol mapper mux txrxdata 2fsk 4fsk gaussian or raised cosine filtering pre- coder 3fsk 2 loop filter fractional_n 08635-039 figure 40. transmit modulation implementation
ADF7021-V rev. 0 | page 25 of 60 setting the transmit data rate in all modulation modes except for oversampled 2fsk mode, an accurate clock is provided on the txrxclk pin to latch the data from the microcontroller into the transmit section at the required data rate. the exact frequency of this clock is defined by 32 = vide cdr_clk_di divide demod_clk_ xtal clkdata where: xtal is the crystal or tcxo frequency. demod_clk_divide is the divider that sets the demodulator clock rate (register 3, bits[db9:db6]). cdr_clk_divide is the divider that sets the cdr clock rate (register 3, bits[db17:db10]). see the register 3transmit/receive clock register section for more programming information. setting the fsk transmit deviation frequency in all modulation modes, the deviation from the center frequency is set using the tx_frequency_deviation bits (register 2, bits[db27:db19]). the deviation from the center frequency in hz is as follows: for direct rf output, 16 2 (hz) o n cy_deviat i tx_freque n pfd f dev = with rf_divide_by_2 (register 1, bit db18) enabled, 16 2 5.0(hz) o n cy_deviat i tx_freque n pfd f dev = where tx_frequency_deviation is a number from 1 to 511 (register 2, bits[db27:db19]). in 4fsk modulation, the four symbols (00, 01, 11, 10) are transmitted as 3 f dev and 1 f dev . binary frequency shift keying (2fsk) binary frequency shift keying is implemented by setting the n value for the center frequency and then toggling it with the txrxdata line. the deviation from the center frequency is set using the tx_frequency_deviation bits (register 2, bits[db27:db19]). 2fsk is selected by setting the modulation_scheme bits (register 2, bits[db6:db4]) to 000. minimum shift keying (msk) or gaussian minimum shift keying (gmsk) is supported by selecting 2fsk modulation and using a modulation index of 0.5. a modulation index of 0.5 is set by configuring register 2, bits[db27:db19] for an f dev = 0.25 transmit data rate. three-level frequency shift keying (3fsk) in three-level fsk modulation3fsk, also known as modified duobinary fsk and as partial response maximum likelihood class 4 (prml4) signalingthe binary data (logic 0 and logic 1) is mapped onto three distinct frequencies: the carrier frequency (f c ), the carrier frequency minus a deviation frequency (f c ? f dev ), and the carrier frequency plus the deviation frequency (f c + f dev ). a logic 0 is mapped to the carrier frequency, whereas a logic 1 is mapped onto either the f c ? f dev frequency or the f c + f dev frequency. f c f c ? f dev f c + f dev rf frequency 0 +1 ?1 08635-040 figure 41. 3fsk symbol -to-frequency mapping compared with 2fsk, this bit-to-frequency mapping results in a reduced transmission bandwidth because some energy is removed from the rf sidebands and transferred to the carrier frequency. at low modulation index, 3fsk improves the trans- mit spectral efficiency by up to 25% when compared with 2fsk. the bit-to-symbol mapping for 3fsk is implemented using a linear convolutional encoder that also permits viterbi detection to be used in the receiver. a block diagram of the transmit hard- ware used to realize this system is shown in figure 42 . the convolutional encoder polynomial used to implement the transmit spectral shaping is p(d) = 1 ? d 2 where: p is the convolutional encoder polynomial. d is the unit delay operator. a digital precoder with transfer function 1/p(d) implements an inverse modulo-2 operation of the 1 ? d 2 shaping filter in the transmitter. precoder 1/p(d) convolutional encoder p(d) fsk mod control and data filtering tx data 0, 1 0, +1, ?1 0, 1 to n divider f c f c + f dev f c ? f dev 08635-041 figure 42. 3fsk encoding
ADF7021-V rev. 0 | page 26 of 60 the signal mapping of the input binary transmit data to the three-level convolutional output is shown in table 9 . the convolutional encoder restricts the maximum number of sequential +1s or ?1s to two and delivers an equal number of +1s and ?1s to the fsk modulator, thus ensuring equal spectral energy in both rf sidebands. table 9. three-level signal mapping of the convolutional encoder txdata 1 0 1 1 0 0 1 0 0 1 precoder output 1 0 0 1 0 1 1 1 1 0 encoder output +1 0 ?1 +1 0 0 +1 0 0 ?1 another property of this encoding scheme is that the trans- mitted symbol sequence is dc-free, which facilitates symbol detection and frequency measurement in the receiver. in addition, no code rate loss is associated with this three-level convolutional encoder; that is, the transmitted symbol rate is equal to the data rate presented at the transmit data input. 3fsk is selected by setting the modulation_scheme bits (register 2, bits[db6:db4]) to 010. it can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal. four-level frequency shift keying (4fsk) in 4fsk modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the tx data bit stream to one of four possible symbols (?3, ?1, +1, +3). thus, the transmitted symbol rate is half the input bit rate. these symbols are mapped to equally spaced discrete frequencies centered on the rf carrier at ?3 f dev , ?1f dev , +1 f dev , and +3 f dev where f dev is programmed using the tx_frequency_ deviation bits (bits[db27:db19] in register 2) and is also equal to half the frequency spacing between adjacent symbols. by minimizing the separation between symbol frequencies, 4fsk can have high spectral efficiency. the bit-to-symbol mapping for 4fsk is gray coded and is shown in figure 43 . tx data symbol frequencies f t +3 f dev + f dev ? f dev ?3 f dev 00011011 08635-042 figure 43. 4fsk bit-to-symbol mapping the inner deviation frequencies (+f dev and ?f dev ) are set using the tx_frequency_deviation bits (bits[db27:db19] in register 2). the outer deviation frequencies are automatically set to three times the inner deviation frequency. the transmit clock from pin txrxclk is available after writing to register 3 in the power-up sequence for receive mode. the msb of the first symbol should be clocked into the ADF7021-V on the first transmit clock pulse from the ADF7021-V after writing to register 3. see figure 6 and figure 7 for more timing information; see figure 54 and figure 55 for the power-up sequences. oversampled 2fsk in oversampled 2fsk, there is no data clock from the txrxclk pin. instead, the transmit data at the txrxdata pin is sampled at 32 times the programmed rate. oversampled 2fsk is the only modulation mode that can be used with the uart mode interface for data transmission (see the interfacing to a microcontroller/dsp section for more information). spectral shaping gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. the ADF7021-V supports gaussian filtering (bandwidth time [bt] = 0.5) on 2fsk modulation. raised cosine filtering can be used with 2fsk, 3fsk, or 4fsk modulation. the roll-off factor (alpha) of the raised cosine filter has programmable options of 0.5 and 0.7. both the gaussian and raised cosine filters are implemented using linear phase digital filter architectures that deliver precise control over the bt and alpha filter parameters, and guarantee a transmit spectrum that is very stable over temperature and supply variation. gaussian frequency shift keying (gfsk) gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. the bt product of the gaussian filter used is 0.5. gaussian filtering can be used only with 2fsk modulation. gfsk is selected by setting register 2, bits[db6:db4] to 001. raised cosine filtering raised cosine filtering provides digital prefiltering of the transmit data by using a raised cosine filter with a roll-off factor (alpha) of either 0.5 or 0.7. the alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7 (set register 2, bit db30 to logic 1). raised cosine filtering can be used with 2fsk, 3fsk, and 4fsk modulation. raised cosine filtering is enabled by setting register 2, bits[db6:db4] as shown in table 10 .
ADF7021-V rev. 0 | page 27 of 60 modulation and filtering options the various modulation and data filtering options for the ADF7021-V are described in table 10 . table 10. modulation and filtering options modulation data filtering register 2, bits[db6:db4] binary fsk 2fsk none 000 msk 1 none 000 oqpsk with half sine baseband shaping 2 none 000 gfsk gaussian 001 gmsk 3 gaussian 001 rc2fsk raised cosine 101 oversampled 2fsk none 100 three-level fsk 3fsk none 010 rc3fsk raised cosine 110 four-level fsk 4fsk none 011 rc4fsk raised cosine 111 1 msk is 2fsk modulation with a modulation index = 0.5. 2 offset quadrature phase shift keying (oqpsk) with half sine baseband shaping is spectrally equivalent to msk. 3 gmsk is gfsk with a modulation index = 0.5. transmit latency transmit latency is the delay time from the sampling of a bit/symbol by the txrxclk signal to when that bit/symbol appears at the rf output. the latency without any data filtering is 1 bit. the addition of data filtering adds a further latency as indicated in table 11 . it is important that the ADF7021-V be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. the ADF7021-V should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme. this ensures that all of the data sampled by the txrxclk signal appears at rf. the figures for latency in table 11 assume that the positive txrxclk edge is used to sample data (default). if the txrxclk is inverted by setting register 2, bits[db29:db28], an additional 0.5 bit latency can be added to all values in table 11 . table 11. bit/symbol latency in transmit mode for various modulation schemes modulation latency 2fsk 1 bit gfsk 4 bits rc2fsk, alpha = 0.5 5 bits rc2fsk, alpha = 0.7 4 bits 3fsk 1 bit rc3fsk, alpha = 0.5 5 bits rc3fsk, alpha = 0.7 4 bits 4fsk 1 symbol rc4fsk, alpha = 0.5 5 symbols rc4fsk, alpha = 0.7 4 symbols test pattern generator the ADF7021-V has a number of built-in test pattern generators that can be used to facilitate radio link setup or rf measurement. a full list of the supported test patterns is shown in table 12 . the data rate for these test patterns is the programmed data rate set in register 3. the pn9 sequence is suitable for test modulation when carrying out adjacent channel power (acp) or occupied bandwidth measurements. table 12. transmit test pattern generator options test pattern register 15, bits[db10:db8] normal 000 transmit carrier only 001 transmit +f dev tone only 010 transmit ?f dev tone only 011 transmit 1010 pattern 100 transmit pn9 sequence 101 transmit swd pattern repeatedly 110
ADF7021-V rev. 0 | page 28 of 60 receiver section rf front end the ADF7021-V is based on a fully integrated, low if receiver architecture. the low if architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. figure 44 shows the structure of the receiver front end. the many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application. to achieve a high level of resilience against spurious reception, the low noise amplifier (lna) features a differential input. switch sw2 shorts the lna input when transmit mode is selected (register 0, bit db27 = 0). this feature facilitates the design of a combined lna/pa matching network, avoiding the need for an external tx/rx switch. see the lna/pa matching section for details on the design of the matching network. sw2 lna rfin rfin tx/rx select (reg 0, bit db27) lna_mode (reg 9, bit db25) lna_bias (reg 9, bits[db27:db26]) mixer_linearity (reg 9, bit db28) lo i (to filter) q (to filter) lna_gain (reg 9, bits[db21:db20]) lna/mixer_enable (reg 8, bit db6) 08635-043 figure 44. rf front end the lna is followed by a quadrature downconversion mixer, which converts the rf signal to the if frequency of 100 khz. an important consideration is that the output frequency of the synthesizer must be programmed to a value 100 khz below the center frequency of the received channel. the lna has two basic operating modes: high gain/low noise mode and low gain/ low power mode. to switch between these two modes, use the lna_mode bit (register 9, bit db25). the mixer is also config- urable for either a low current mode or an enhanced linearity mode using the mixer_linearity bit (register 9, bit db28). based on the specific sensitivity and linearity requirements of the application, it is recommended that the lna_mode bit and the mixer_linearity bit be adjusted as shown in tabl e 14 . the gain of the lna is configured by the lna_gain bits (register 9, bits[db21:db20]) and can be set by the user or by the automatic gain control (agc) logic. if filter if filter settings out-of-band interference is rejected by means of a fifth-order butterworth polyphase if filter centered on a frequency of 100 khz. the bandwidth of the if filter can be programmed to 9 khz, 13.5 khz, or 18.5 khz in register 4, bits[db31:db30], and should be chosen as a compromise between interference rejection and attenuation of the desired signal. if the agc loop is disabled, the gain of the if filter can be set to one of three levels by using the filter_gain bits (register 9, bits[db23:db22]). the filter gain is adjusted automatically if the agc loop is enabled. if filter bandwidth and center frequency calibration to compensate for manufacturing tolerances, the if filter should be calibrated after power-up to ensure that the bandwidth and center frequency are correct. coarse and fine calibration schemes are provided to offer a choice between fast calibration (coarse calibration) and high filter centering accuracy (fine calibration). coarse calibration is enabled by setting register 5, bit db4 high. fine calibration is enabled by setting register 6, bit db4 high. for details on when it is necessary to perform a filter calibration, and in what applications to use either a coarse calibration or fine calibration, see the if filter bandwidth calibration section. rssi/agc the rssi is implemented as a successive compression log amp following the baseband (bb) channel filtering. the log amp achieves 3 db log linearity. it also doubles as a limiter to convert the signal-to-digital levels for the fsk demodulator. the offset correction circuit uses the bbos_clk_divide bits (bits db5:db4] in register 3) and should be set between 1 mhz and 2 mhz. the rssi level is converted for user readback and for digitally controlled agc by an 80-level (7-bit) flash adc. this level can be converted to input power in dbm. by default, the agc is on when powered up in receive mode. 1 ifwr ifwr ifwr ifwr latch aaa r clk adc offset correction rssi fsk demod 08635-044 figure 45. rssi block diagram rssi thresholds when the rssi is above agc_high_threshold (register 9, bits[db17:db11]), the gain is reduced. when the rssi is below agc_low_threshold (register 9, bits[db10:db4]), the gain is increased. the thresholds default to 70 (high threshold) and 30 (low threshold) on power-up in receive mode. a delay (set by agc_clk_divide in register 3, bits[db31:db26]) is programmed to allow for settling of the loop. a value of 33 is recommended to give an agc update rate of 3 khz. the user has the option of changing the two threshold values from the defaults of 70 and 30 (register 9). the default agc setup values should be adequate for most applications. the threshold values must be more than 30 apart for the agc to operate correctly.
ADF7021-V rev. 0 | page 29 of 60 offset correction clock in register 3, the user should set the bbos_clk_divide bits (bits[db5:db4]) to give a baseband offset clock (bbos clk) frequency between 1 mhz and 2 mhz. bbos clk (hz) = xtal/(bbos_clk_divide) where bbos_clk_divide can be set to 4, 8, 16, or 32. agc information and timing agc is selected by default and operates by setting the appro- priate lna and filter gain settings for the measured rssi level. to enter one of the lna/mixer modes listed in table 14 , the user can disable agc by writing to register 9. after each gain change, the agc loop waits for a programmed time to allow transients to settle. this agc update rate is set according to agc update rate (hz) = divide clkagc divide clkseq __ (hz) __ where: seq_clk_divide = 100 khz (register 3, bits[db25:db18]). agc_clk_divide is set by register 3, bits[db31:db26]. a value of 33 is recommended. it is recommended that agc_clk_divide be set to a value of 33, which allows a settling time of 333 s for each gain change. by using the recommended setting for agc_clk_divide , the total agc settling time is (hz) (sec) rateupdate agc changes gainagcofnumber time settling agc = the total afc settling time depends on the number of agc gain changes during reception of a packet. a total of five gain changes gives a worst-case agc settling time of 5 333 s. to allow for agc settling, the preamble length should be adjusted accordingly. rssi formula (converting to dbm) the rssi formula is input power (dbm) = (?130 dbm + ( readback code + gain mode correction )) 0.5 where: readback code is given by bit rv7 to bit rv1 in the readback register (see figure 57 and the readback format section). gain mode correction is given by the values in table 13 . the lna gain (lg2, lg1) and filter gain (fg2, fg1) values are also obtained from the readback register, as part of an rssi readback. table 13. gain mode correction lna gain (lg2, lg1) filter gain (fg2, fg1) gain mode correction h (1, 0) h (1, 0) 0 m (0, 1) h (1, 0) 24 m (0, 1) m (0, 1) 38 m (0, 1) l (0, 0) 58 l (0, 0) l (0, 0) 86 an additional factor should be introduced to account for losses in the front-end-matching network/antenna. table 14. lna/mixer modes (register 9 settings) receiver mode lna_mode (bit db25) lna_gain (bits[db21:db20]) mixer_linearity (bit db28) sensitivity (2fsk, data rate = 4.8 kbps, f dev = 4 khz) (dbm) rx current consumption (ma) input ip3 (dbm) high sensitivity mode (default) 0 30 0 ?116.5 20.1 ?24 enhanced linearity, high gain 0 30 1 ?113 20.1 ?20 medium gain 1 10 0 ?108 17.9 ?13.5 enhanced linearity, medium gain 1 10 1 ?102 17.9 ?9 low gain 1 3 0 ?99 17.9 ?5 enhanced linearity, low gain 1 3 1 ?91 17.9 ?3
ADF7021-V rev. 0 | page 30 of 60 demodulation, detection, and cdr system overview an overview of the demodulation, detection, and clock and data recovery (cdr) of the received signal on the ADF7021-V is shown in figure 46 . i q limiters viterbi detection mux clock and data recovery txrxdata txrxclk correlator demodulator post demod filter linear demodulator mux 3fsk threshold detection 2fsk/3fsk/4fsk 08635-045 figure 46. overview of demodulation, detection, and cdr process the quadrature outputs of the if filter are first limited and then fed to either the correlator fsk demodulator or to the linear fsk demodulator. the correlator demodulator is used to demodulate 2fsk, 3fsk, and 4fsk. the linear demodulator is used for frequency measurement and is enabled when the afc loop is active. the linear demodulator can also be used to demodulate 2fsk. following the demodulator, a digital postdemodulator filter removes excess noise from the demodulator signal output. threshold/slicer detection is used for data recovery of 2fsk and 4fsk. data recovery of 3fsk can be implemented using either threshold detection or viterbi detection. an on-chip cdr pll is used to resynchronize the received bit stream to a local clock. it outputs the retimed data and clock on the txrxdata and txrxclk pins, respectively. correlator demodulator the correlator demodulator can be used for 2fsk, 3fsk, and 4fsk demodulation. figure 47 shows the operation of the correlator demodulator for 2fsk. if ? f dev if + f dev i if q limiters reg 4, bits[db19:db10] reg 4, bit db7 dot_product frequency cor r elator discriminator_bw reg 4, bits[db9:db8] rx_invert discrim bw 2fsk = +1, ?1 3fsk = +1, 0, ?1 4fsk = +3, +1, ?1, ?3 output levels: 0 8635-046 figure 47. 2fsk correlator fsk demodulator operation the quadrature outputs of the if filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2fsk/3fsk/4fsk spectrum. for 2fsk modulation, data is recovered by comparing the output levels from two correlators. the performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white gaussian noise (awgn). this method of fsk demodulation provides approximately 3 db to 4 db better sensitivity than a linear demodulator. linear demodulator figure 48 shows a block diagram of the linear demodulator. post demod filter envelope detector slicer 2fsk frequency if level i q limiters linear discriminator reg 4, bits[db29:db20] frequency readback and afc loop + 2fsk rxdata rxclk 08635-047 figure 48. block diagram of linear fsk demodulator a digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. the discriminator output is filtered and averaged using a com- bined averaging filter and envelope detector. the demodulated 2fsk data from the postdemodulator filter is recovered by slicing against the output of the envelope detector, as shown in figure 48 . this method of demodulation corrects for frequency errors between the transmitter and receiver when the received spectrum is close to or within the if bandwidth. this envelope detector output is also used for afc readback and provides the frequency estimate for the afc control loop. postdemodulator filter a second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. the bandwidth of this postdemodulator filter is programmable and must be optimized for the users data rate and the received modulation type. if the bandwidth is too narrow, performance degrades due to intersymbol interference (isi). if the bandwidth is too wide, excess noise degrades the performance of the receiver. the post_demod_bw bits (register 4, bits[db29:db20]) set the bandwidth of this filter.
ADF7021-V rev. 0 | page 31 of 60 2fsk bit slicer/threshold detection 2fsk demodulation can be implemented using the correlator fsk demodulator or the linear fsk demodulator. in both cases, threshold detection is used for data recovery at the output of the postdemodulator filter. the output signal levels of the correlator demodulator are always centered about 0. therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. this results in robust data recovery that does not suffer from the classic baseline wander problems that exist in more traditional fsk demodulators. when the linear demodulator is used for 2fsk demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the if filter bandwidth. 3fsk and 4fsk threshold detection 4fsk demodulation is implemented using the correlator demodulator followed by the postdemodulator filter and threshold detection. the output of the postdemodulator filter is a four-level signal that represents the transmitted symbols (?3, ?1, +1, +3). threshold detection of 4fsk requires three threshold settings: one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3fsk/4fsk_slicer_threshold bits (register 13, bits[db10:db4]). 3fsk demodulation is implemented using the correlator demod- ulator, followed by a postdemodulator filter. the output of the postdemodulator filter is a three-level signal that represents the transmitted symbols (?1, 0, +1). data recovery of 3fsk can be implemented using threshold detection or viterbi detection. threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below 0 using the 3fsk/4fsk_slicer_threshold bits (register 13, bits[db10:db4]). 3fsk viterbi detection viterbi detection of 3fsk operates on a four-state trellis and is implemented using two interleaved viterbi detectors operating at half the symbol rate. the viterbi detector is enabled by register 13, bit db11. to facilitate different run-length constraints in the transmitted bit stream, the viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the viterbi_ path_memory bits (register 13, bits[db14:db13]). this value should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. when used with viterbi detection, the receiver sensitivity for 3fsk is typically 3 db greater than that obtained using threshold detection. when the viterbi detector is enabled, however, the receiver bit latency is increased by twice the viterbi path memory length. clock and data recovery (cdr) an oversampled digital clock and data recovery (cdr) pll is used to resynchronize the received bit stream to a local clock in all modulation modes. the oversampled clock rate of the pll (cdr clk) must be set at 32 times the symbol rate (see the register 3transmit/receive clock register section). the maxi- mum data/symbol rate tolerance of the cdr pll is determined by the number of zero-crossing symbol transitions in the trans- mitted packet. for example, if using 2fsk with a 101010 preamble, a maximum tolerance of 3.0% of the data rate is achieved. however, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. to maximize the data rate tolerance of the cdr, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. for example, using 2fsk with manchester-encoded data achieves a data rate tolerance of 2.0%. the cdr pll is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchro- nization within five-symbol transitions of preamble. in 4fsk modulation, the tolerance using the +3, ?3, +3, ?3 preamble is 3% of the symbol rate (or 1.5% of the data rate). however, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. to maximize the symbol/data rate tolerance of the cdr, the remainder of the 4fsk packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scram- bling and/or by inserting specific dc-balancing symbols into the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. in 3fsk modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. however, tx data scrambling is recommended to limit the run length of 0 symbols in the transmit bit stream. using 3fsk, the cdr data rate tolerance is typically 0.5%.
ADF7021-V rev. 0 | page 32 of 60 receiver setup correlator demodulator setup to enable the correlator for various modulation modes, see table 15 . table 15. enabling the correlator demodulator received modulation demod_scheme (register 4, bits[db6:db4]) 2fsk 001 3fsk 010 4fsk 011 to optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modula- tion used by the transmitter. the discriminator bandwidth is controlled by register 4, bits[db19:db10], and is defined as ( ) 3 10400 _ = kclk demod bwtor discrimina where: demod clk is as defined in the register 3transmit/receive clock register section. k is set for each modulation mode as follows: for 2fsk, ? ? ? ? ? ? ? ? = dev f roundk 3 10100 for 3fsk, ? ? ? ? ? ? ? ? = dev f roundk 2 10100 3 for 4fsk, ? ? ? ? ? ? ? ? = dev 4fsk f roundk 4 10100 3 where: round is rounded to the nearest integer. round 4fsk is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. f dev is the transmit frequency deviation in hz. for 4fsk, f dev is the frequency deviation used for the 1 symbols (that is, the inner frequency deviations). to optimize the coefficients of the correlator, register 4, bit db7 and register 4, bits[db9:db8] must also be assigned. the value of these bits depends on whether k is odd or even. these bits are assigned according to table 16 and table 17 . table 16. assignment of correlat or k value for 2fsk and 3fsk k k/2 (k + 1)/2 register 4, bit db7 register 4, bits[db9:db8] even even n/a 0 00 even odd n/a 0 10 odd n/a even 1 00 odd n/a odd 1 10 table 17. assignment of correlator k value for 4fsk k register 4, bit db7 register 4, bits[db9:db8] even 0 00 odd 1 00 linear demodu lator setup the linear demodulator can be used for 2fsk demodulation. to enable the linear demodulator, set the demod_scheme bits (register 4, bits[db6:db4]) to 000. postdemodulator filter setup the 3 db bandwidth of the postdemodulator filter should be set according to the received modulation type and data rate. the bandwidth is controlled by register 4, bits[db29:db20] and is given by clk demod f bw demod post cutoff = 2 __ 11 where f cutoff is the target 3 db bandwidth in hz of the post- demodulator filter. table 18. postdemodulator filter bandwidth settings for 2fsk/3fsk/4fsk modulation schemes received modulation postdemodulator filter bandwidth, f cutoff (hz) 2fsk 0.75 data rate 3fsk 1 data rate 4fsk 1.6 symbol rate (0.8 data rate) 3fsk viterbi detector setup the viterbi detector can be used for 3fsk data detection; it is activated by setting register 13, bit db11, to logic 1. the viterbi path memory length is programmable in steps of 4, 6, 8, or 32 bits (viterbi_path_memory, register 13, bits[db14:db13]). the path memory length should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. the viterbi detector also uses threshold levels to implement the maximum likelihood detection algorithm. these thresholds are programmable via the 3fsk/4fsk_slicer_threshold bits (register 13, bits[db10:db4]). these bits are assigned as follows: 3fsk/4fsk_slicer_threshold = ? ? ? ? ? ? ? ? 3 10100 _ _ 75 k deviation frequency tx where k is the value calculated for correlator discriminator bandwidth. 3fsk threshold detector setup to activate threshold detection of 3fsk, register 13, bit db11, should be set to logic 0. the 3fsk/4fsk_slicer_threshold bits (register 13, bits[db10:db4]) should be set as described in the 3fsk viterbi detector setup section.
ADF7021-V rev. 0 | page 33 of 60 3fsk cdr setup in 3fsk, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the cdr to acquire lock. the clock and data recovery for 3fsk requires a number of parameters in register 13 to be set (see table 19 ). 4fsk threshold detector setup the threshold for the 4fsk detector is set using the 3fsk/4fsk_slicer_threshold bits (register 13, bits[db10:db4]). the threshold should be set as follows: 3fsk/4fsk_slicer_threshold = ? ? ? ? ? ? ? ? 3 10100 78 k deviation tx outer 4fsk where k is the value calculated for correlator discriminator bandwidth. fsk demodulator optimization 2fsk preamble the recommended preamble bit pattern for 2fsk, gfsk, and rc2fsk is a dc-free pattern (such as a 10101010 pattern). preamble patterns with longer run-length constraints (such as 11001100) can also be used, but result in a longer synchro- nization time of the received bit stream in the receiver. the preamble must allow enough bits for agc settling of the receiver and cdr acquisition (see table 20 ). the remaining fields that follow the preamble do not need to use dc-free coding. for these fields, the ADF7021-V can accom- modate coding schemes with a run length of greater than eight bits without any performance degradation. refer to the an-915 application note for more information. 4fsk preamble and data coding the recommended preamble bit pattern for 4fsk is a repeating 00100010 bit sequence. this two-level sequence of repeating ?3, +3, ?3, +3 symbols is dc-free and maximizes the symbol timing performance and data recovery of the 4fsk preamble in the receiver. the minimum recommended length of the preamble is 32 bits (16 symbols). the remainder of the 4fsk packet should be constructed so that the transmitted symbols retain close to a dc-free balance by using data scrambling and/or by inserting specific dc-balancing symbols in the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. table 19. 3fsk cdr settings parameter (register 13) recommended setting purpose phase_correction (bit db12) 1 phase correction is on 3fsk_cdr_threshold (bits[db21:db15]) ? ? ? ? ? ? ? ? 3 10100 _ _ 62 k deviation frequency tx where k is the value calculated for correlator discriminator bandwidth. sets cdr decision threshold levels 3fsk_preamble_time_validate (bits[db25:db22]) 15 preamble detector time qualifier table 20. preamble bit length for 2fsk modulation demodulator sensitivity degradation from specifications rx frequency error tolerance (1 per) minimum preamble (bits) correlator (afc off ) mod index = 2 0 db 30% f dev 16 mod index = 1 0 db 25% f dev 16 mod index = 0.5 0 db 20% f dev 16 linear (afc off ) f dev = 4.2 khz 3 db 0.5 ifbw 1 64 f dev = 2.2 khz 3 db 0.5 ifbw 1 112 f dev = 1.6 khz 3 db 0.5 ifbw 1 128 correlator (afc on) 2 db afc pull-in range 2 96 to 128 3 linear (afc on) 3 db afc pull-in range 2 96 to 128 correlator + bypass cdr (afc off ) 2 db to 3 db 4 50% f dev 5 8 1 this value is generally true; however, some sensitivity degradation may occur close to the edge of the if filter. 2 limited to 0.5 ifbw or afc pu ll-in range, whichever is less. 3 dependent on modulation index and f dev . at higher modulation indexes (1.0 or greater) and higher f dev (>4.0 khz), the minimum preamble length is 96 bits. the minimum preamble length increases as the modulation index and f dev are reduced. 4 dependent on the perfor mance of the symbol timing recovery modu le on the external microcontroller. 5 depends on the pulse width mark/space ratio of logic 1 to logi c 0 that the symbol timing recove ry scheme on the external micro controller can tolerate. in this mode, the mark/space ratio of the recovered bit stream increases with frequency error. in the absence of frequency error, the mark/sp ace ratio is 50:50, that is, the width of a logic 1 is the same as the width of a logic 0.
ADF7021-V rev. 0 | page 34 of 60 correlator demodulator and low modulation indexes the modulation index in 2fsk is defined as ratedata f index modulation dev = 2 the receiver sensitivity performance and receiver frequency tolerance can be maximized at low modulation indexes by increasing the discriminator bandwidth of the correlator demodulator. for modulation indexes of less than 0.4, it is recommended that the correlator bandwidth be doubled by calculating k as follows: ? ? ? ? ? ? ? ? = dev f roundk 2 100 3 the discriminator_bw value in register 4 should be recalculated using the new k value. figure 29 illustrates the improved sensitivity that can be achieved for 2fsk modulation, at low modulation indexes, by doubling the correlator bandwidth. afc operation the ADF7021-V also supports a real-time afc loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/tcxos. the afc loop uses the linear frequency discriminator block to estimate frequency errors. the linear fsk discriminator output is filtered and averaged to remove the fsk frequency modulation using a combined averaging filter and envelope detector. in receive mode, the output of the envelope detector provides an estimate of the average if frequency. the two methods of afc supported on the ADF7021-V are external afc and internal afc. external afc with external afc, the user reads back the frequency infor- mation through the ADF7021-V serial port and applies a frequency correction value to the synthesizer-n divider. the frequency information is obtained by reading the signed, 16-bit afc readback value, as described in the readback format section, and by applying the following formula: frequency readback (hz) = ( afc readback demod clk )/2 18 although the afc readback value is a signed number, under normal operating conditions, it is positive. in the absence of frequency errors, the frequency readback value is equal to the if frequency of 100 khz. internal afc the ADF7021-V supports a real-time, internal, automatic frequency control loop. in this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-n divider using an internal proportional integral (pi) control loop. the internal afc control loop parameters are controlled in register 10. the internal afc loop is activated by setting bit db4 in register 10 to 1. a scaling coefficient must also be entered, based on the crystal frequency in use. this is set up using bits[db16:db5] in register 10 and should be calculated as follows: ? ? ? ? ? ? ? ? = xtal round factor scaling afc 5002 _ _ 24 maximum afc range the maximum frequency correction range of the afc loop is programmable using register 10, bits[db31:db24]. the maximum afc correction range is the difference in frequency between the upper and lower limits of the afc tuning range. for example, if the maximum afc correction range is set to 10 khz, the afc can adjust the receiver lo within the f lo 5 khz range. however, when rf_divide_by_2 (register 1, bit db18) is enabled, the programmed range is halved. the user should account for this halving by doubling the programmed maxi- mum afc range. the recommended maximum afc correction range should be 1.5 if filter bandwidth. if the maximum frequency correction range is set to be >1.5 if filter bandwidth, the attenuation of the if filter can degrade the afc loop sensitivity. the adjacent channel rejection (acr) performance of the receiver can be degraded when afc is enabled and the afc correction range is close to or greater than the if filter bandwidth. however, because the afc correction range is programmable, the user can trade off afc correction range and acr performance of the receiver. when afc errors are removed using either the internal or external afc, further improvement in receiver sensitivity can be obtained by reducing the if filter bandwidth using the if_filter_bw bits (register 4, bits[db31:db30]).
ADF7021-V rev. 0 | page 35 of 60 automatic sync word detection (swd) the ADF7021-V also supports automatic detection of the sync or id fields. to activate this mode, the sync (or id) word must be preprogrammed into the ADF7021-V. in receive mode, this preprogrammed word is compared to the received bit stream. when a valid match is identified, the external swd pin is asserted by the ADF7021-V on the next rx clock pulse. this feature can be used to alert the microprocessor that a valid channel has been detected. it relaxes the computational requirements of the microprocessor and reduces the overall power consumption. the swd signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. the data packet length can be set in register 12, bits[db15:db8]. the swd pin status can be configured by setting bits[db7:db6] in register 12. bits[db5:db4] in register 11 are used to set the length of the sync/id word, which can be 12, 16, 20, or 24 bits long. a value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when a noise/no signal is present at the receiver input. the transmitter must transmit the sync byte msb first, lsb last to ensure proper alignment in the receiver sync-byte-detection hardware. an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. the error tolerance value is assigned in register 11, bits[db7:db6].
ADF7021-V rev. 0 | page 36 of 60 applications information if filter bandwidth calibration the if filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. the automatic calibration requires no external intervention when it is initiated by a write to register 5. depending on numerous factors, such as if filter bandwidth, received signal bandwidth, and temperature varia- tion, the user must determine whether to carry out a coarse calibration or a fine calibration. the performance of both calibration methods is shown in table 21 . table 21. if filter calibration specifications filter calibration method center frequency accuracy 1 calibration time (typ) coarse calibration 100 khz 2.5 khz 200 s fine calibration 100 khz 0.6 khz 8.2 ms 1 after calibration. calibration setup if filter calibration is initiated by writing to register 5 and setting the if_cal_coarse bit (bit db4). this initiates a coarse filter calibration. if the if_fine_cal bit (register 6, bit db4) has already been set high, the coarse calibration is followed by a fine calibration; otherwise, the calibration ends. when initiated by writing to the part, calibration is performed automatically without user intervention. the calibration time is 200 s for coarse calibration and 8.2 ms for fine calibration, during which time the ADF7021-V should not be accessed. the if filter calibration logic requires that the if_filter_divider bits (register 5, bits[db13:db5]) be set such that khz50 __ (hz) = divider filterif xtal the fine calibration uses two internally generated tones at certain offsets around the if filter. the two tones are attenuated by the if filter, and the level of this attenuation is measured using the rssi. the filter center frequency is adjusted to allow equal attenuation of both tones. the attenuation of the two test tones is then remeasured. this process continues for a maximum of 10 rssi measurements, at which point the calibration algorithm sets the if filter center frequency to within 0.6 khz of 100 khz. the frequency of these tones is set in register 6 by the if_cal_lower_tone_divide bits (bits[db12:db5]) and the if_cal_upper_tone_divide bits (bits[db20:db13]), as shown in the following equations. lower tone frequency (khz) = 2 vide er_tone_di if_cal_low xtal upper tone frequency (khz) = 2 vide er_tone_di if_cal_upp xtal it is recommended that the lower tone and the upper tone be set as shown in table 22 . table 22. if filter fine calibration tone frequencies if filter bandwidth (khz) lower tone frequency (khz) upper tone frequency (khz) 9 78.1 116.3 13.5 79.4 116.3 18.5 78.1 119 because the filter attenuation is slightly asymmetrical, it is necessary to have a small offset in the filter center frequency to provide near equal rejection at the upper and lower adjacent channels. the calibration tones listed in table 22 provide this small positive offset in the if filter center frequency. in some applications, an offset may not be required, and the user may wish to center the if filter at 100 khz exactly. in this case, the user can alter the tone frequencies from those given in table 22 to adjust the fine calibration result. the calibration algorithm adjusts the filter center frequency and measures the rssi 10 times during the calibration. the time for an adjustment plus rssi measurement is given by clkseq ll_time if_cal_dwe timencalibratio toneif = it is recommended that the if tone calibration time be at least 800 s. the total time for the if filter fine calibration is given by if filter fine calibration time = if tone calibration time 10 when to use coarse calibration it is recommended that a coarse calibration be performed on every power-up in receive mode. this calibration typically takes 200 s. the filter_cal_complete signal from muxout (set using bits[db31:db29] in register 0) can be used to monitor the filter calibration duration or to signal the end of calibration. the ADF7021-V should not be accessed during calibration.
ADF7021-V rev. 0 | page 37 of 60 when to use fine calibration in cases where the receive signal bandwidth is very close to the bandwidth of the if filter, it is recommended that a fine filter calibration be performed every time that the unit powers up in receive mode. a fine calibration should be performed if obw + coarse calibration variation > if_filter_bw where: obw is the 99% occupied bandwidth of the transmit signal. coarse calibration variation is 2.5 khz. if_filter_bw is set by register 4, bits[db31:db30]. the filter_cal_complete signal from muxout (set by register 0, bits[db31:db29]) can be used to monitor the filter calibration duration or to signal the end of calibration. a coarse filter calibration is automatically performed prior to a fine filter calibration. when to use single fine calibration in applications where the receiver powers up numerous times in a short period, it is necessary to perform fine calibration only once, on the initial power-up in receive mode. after the initial coarse calibration and fine calibration, the result of the fine calibration can be read back through the serial inter- face using the filter_cal_readback result (see the filter bandwidth calibration readback section). on subsequent power-ups in receive mode, the filter is manually adjusted using the previous fine filter calibration result. this manual adjustment is performed using the if_filter_adjust bits (register 5, bits[db19:db14]). this method should only be used if the successive power-ups in receive mode are over a short duration, during which time there is little variation in temperature (<15c). if filter variation with temperature when calibrated, the filter center frequency can vary with changes in temperature. if the ADF7021-V is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. this variation is typically 1 khz per 20c, which means that if a coarse filter calibration and fine filter calibration are performed at 25c, the initial maximum error is 0.5 khz, and the maximum possible change in the filter center frequency over temperature (?40c to +85c) is 3.25 khz. this gives a total error of 3.75 khz. if the receive signal occupied bandwidth is considerably narrower than the if filter bandwidth, the variation of filter center frequency over the operating temperature range may not be an issue. however, if the if filter bandwidth is not wide enough to tolerate the variation with temperature, a periodic filter calibration can be performed or, alternatively, the on-chip temperature sensor can be used to determine when a filter cali- bration is necessary by monitoring for changes in temperature. lna/pa matching the ADF7021-V exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its rf input and output ports are properly matched to the antenna impedance. for cost-sensitive applications, the ADF7021-V is equipped with an internal tx/rx switch that facilitates the use of a simple, combined passive lna/pa matching network. alternatively, an external tx/rx switch such as the adg919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. internal tx/rx switch figure 49 shows the ADF7021-V in a configuration where the internal tx/rx switch is used with a combined lna/pa matching network. this is the configuration used on the eval-ADF7021-Vdbxz evaluation board. for most applica- tions, the slight performance degradation of 1 db to 2 db caused by the internal tx/rx switch is acceptable, allowing the user to take advantage of the cost-saving potential of this solution. the design of the combined matching network must compensate for the reactance presented by the networks in the tx and the rx paths, taking the state of the tx/rx switch into consideration. pa lna rfout rfin rfin v bat l1 ADF7021-V optional bpf or lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin a ntenn a 08635-048 figure 49. ADF7021-V with internal tx/rx switch the procedure typically requires several iterations until an accept- able compromise is reached. the successful implementation of a combined lna/pa matching network for the ADF7021-V is critically dependent on the availability of an accurate electrical model for the pcb. in this context, the use of a suitable cad package is strongly recommended. to avoid this effort, a small form-factor reference design for the ADF7021-V is provided, including matching and harmonic filter components. the design is on a 4-layer pcb. gerber files are available at www.analog.com .
ADF7021-V rev. 0 | page 38 of 60 external tx/rx switch figure 50 shows a configuration using an external tx/rx switch. this configuration allows independent optimization of the matching and filter network in the transmit and receive paths. therefore, it is more flexible and less difficult to design than the configuration using the internal tx/rx switch. the pa is biased through inductor l1, whereas c1 blocks dc current. together, l1 and c1 form the matching network that transforms the source impedance into the optimum pa load impedance, z opt _pa. pa lna rfout rfin rfin v bat l1 ADF7021-V adg919 optional bpf (saw) optional lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin antenna rx/tx ? select 08635-049 figure 50. ADF7021-V with external tx/rx switch z opt _pa depends on various factors, such as the required out- put power, the frequency range, the supply voltage range, and the temperature range. selecting an appropriate z opt _pa helps to minimize the tx current consumption in the application. the an-764 application note and the an-859 application note contain a number of z opt _pa values for representative conditions. under certain conditions, however, it is recom- mended that a suitable z opt _pa value be obtained by means of a load-pull measurement. due to the differential lna input, the lna matching network must be designed to provide both a single-ended-to-differential conversion and a complex, conj ugate impedance match. the net- work with the lowest component count that can satisfy these requirements is the configuration shown in figure 50 , consist- ing of two capacitors and one inductor. depending on the antenna configuration, the user may need a harmonic filter at the pa output to satisfy the spurious emission requirement of the applicable government regulations. the har- monic filter can be implemented in various ways, for example, a discrete lc pi or t-stage filter. the immunity of the ADF7021-V to strong out-of-band interference can be improved by adding a band-pass filter in the rx path. alternatively, the ADF7021-V blocking performance can be improved by selecting one of the enhanced linearity modes, as described in table 14 . image rejection calibration the image channel in the ADF7021-V is 200 khz below the desired signal. the polyphase filter rejects this image with an asymmetric frequency response. the image rejection (ir) performance of the receiver is dependent on how well matched the i and q signals are in amplitude and how well matched the quadrature is between them (that is, how close to 90 apart they are). the uncalibrated image rejection performance is approxi- mately 29 db (at 460 mhz). however, it is possible to improve this performance by as much as 20 db by finding the optimum i/q gain and phase adjust settings. calibration using internal rf source with the lna powered off, an on-chip generated, low level rf tone is applied to the mixer inputs. the lo is adjusted to make the tone fall at the image frequency where it is attenuated by the image rejection of the if filter. the power level of this tone is then measured using the rssi readback. the i/q gain and phase adjust dacs (register 5, bits[db31:db20]) are adjusted and the rssi is remeasured. this process is repeated until the optimum values for the gain and phase adjust are found that provide the lowest rssi readback level, thereby maximizing the image rejection performance of the receiver. using the internal rf source, the rf frequencies that can be used for image calibration are programmable and are odd multiples of the reference frequency. calibration using external rf source ir calibration can also be implemented using an external rf source. the ir calibration procedure is the same as that used for the internal rf source, except that an rf tone is applied to the lna input. calibration proc edure and setup the ir calibration algorithm available from analog devices, inc., is based on a low complexity, 2d optimization algorithm that can be implemented in an external microprocessor or microcontroller. to enable the internal rf source, the ir_cal_source_drive_ level bits (register 6, bits[db29:db28]) should be set to the maximum level. the lna should be set to its minimum gain setting, and the agc should be disabled if the internal rf source is being used. alternatively, an external rf source can be used. the magnitude of the phase adjust is set using the ir_phase_ adjust_mag bits (register 5, bits[db23:db20]). this correc- tion can be applied to either the i or q channel, depending on the value of the ir_phase_adjust_direction bit (register 5, bit db24). the magnitude of the i/q gain is adjusted using the ir_gain_ adjust_mag bits (register 5, bits[db29:db25]). this correction can be applied to either the i or q channel, depending on the value of the ir_gain_adjust_i/q bit (register 5, bit db30), whereas the ir_gain_adjust_up/dn bit (register 5, bit db31) sets whether the gain adjustment defines a gain or an attenuation adjust.
ADF7021-V rev. 0 | page 39 of 60 internal signal source mux rfin lna ADF7021-V polyphase if filter phase adjust gain adjust i q from lo gain adjust register 5 phase adjust register 5 serial interface 4 microcontroller 4 rssi/ log amp 7-bit adc rssi readback i/q gain/phase adjust and rssi measurement algorithm 0 8635-050 rfin figure 51. image rejection calibration using the internal calibration source and a microcontroller the calibration results are valid over changes in the ADF7021-V supply voltage. however, there is some variation with temperature. a typical plot of variation in image rejection over temperature after initial calibrations at ?40c, +25c, and +85c is shown in figure 52 . the internal temperature sensor on the ADF7021-V can be used to determine whether a new ir calibration is required. 0 10 20 30 40 50 60 ?60 ?40 ?20 0 20 40 60 80 100 v dd = 3.0v ifbw = 25khz wanted signal: rf freq = 430mhz modulation = 2fsk data rate = 9.6kbps, data = prbs9 f dev = 4khz level= ?100dbm interferer signal: rf freq = 429.8mhz modulation = 2fsk data rate = 9.6kbps, data = prbs11 f dev = 4khz temperature (c) image rejection (db) cal at +25c cal at +85c cal at ?40c 08635-051 figure 52. image rejection vs. temperature after initial calibrations at ?40c, +25c, and +85c packet structure and coding the suggested packet structure to use with the ADF7021-V is shown in figure 53 . preamble sync word id field data field crc 08635-052 figure 53. typical format of a transmit protocol see the receiver setup section for information about the required preamble structure and length for the various modulation schemes. programming after initial power-up table 23 lists the minimum number of writes needed to set up the ADF7021-V in either tx or rx mode after ce is brought high for a minimum of 100 s before programming any register. additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling afc. when going from tx to rx or vice versa, the user needs to toggle the tx/rx bit and write only to register 0 to alter the lo by 100 khz. table 23. minimum register writes required for tx/rx setup mode required register writes tx reg 1, reg 3, reg 0, reg 2 rx reg 1, reg 3, reg 5, reg 0, reg 4 tx to rx and rx to tx reg 0
ADF7021-V rev. 0 | page 40 of 60 the recommended programming sequences for transmit and receive are shown in figure 54 and figure 55 , respectively. the difference in the power-up routine for a tcxo and xtal reference is shown in these figures. write to register 1 write to register 3 (turns on tx/rx clocks) ce low power-down tx mode 08635-053 power-down ce low turn on external vco and allow adequate settling xtal reference tcxo reference ce high wait 50s (regulator power-up) check for regulator ready ce high wait 50s + 1ms (regulator power-up + typical xtal settling) check for regulator ready write to register 0 (turns on pll) wait 40s (typical pll settling) write to register 2 (turns on pa) wait for pa to ramp up (only if pa ramp enabled) wait for tx latency number of bits (refer to table 11) write to register 2 (turns off pa) wait for pa to ramp down optional. only necessary if pa ramp-down is required. figure 54. power-up sequence for transmit mode
ADF7021-V rev. 0 | page 41 of 60 write to register 6 (sets up if filter fine calibration) rx mode write to register 4 (turns on demod) write to register 10 (turns on afc) optional. write to register 1 08635-054 power-down ce low turn on external vco and allow adequate settling tcxo reference xtal reference optional: only necessary if if filter fine calibration is required. optional: only necessary if swd is required. optional: only necessary if afc is required. write to register 3 (turns on tx/rx clocks) write to register 5 (starts if filter calibration) wait 0.2ms (coarse cal) or wait 8.2ms (coarse calibration + fine calibration) write to register 11 (set up swd) write to register 12 (enable swd) write to register 0 (turns on pll) wait 40s (typical pll settling) ce low power-down ce high wait 50s (regulator power-up) check for regulator ready ce high wait 50s + 1ms (regulator power-up + typical xtal settling) check for regulator ready figure 55. power-up sequence for receive mode
ADF7021-V rev. 0 | page 42 of 60 applications circuit the ADF7021-V requires very few external components for operation. figure 56 shows the recommended application circuit. note that the power supply decoupling and regulator capacitors are omitted for clarity. for recommended component values, see the ADF7021-V evaluation board data sheet and the an-859 application note, accessible from the ADF7021-V product page. follow the refer- ence design schematic closely to ensure optimum performance in narrow-band applications. 48 47 46 45 44 43 42 41 40 39 38 37 ADF7021-V vcoin creg1 vdd1 rfout rfgnd rfin rfin r lna vdd4 rset creg4 gnd4 cvco gnd1 l1 gnd l2 vdd cpout creg3 vdd3 osc1 osc2 muxout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce clkout txrxdata txrxclk swd vdd2 creg2 adcin gnd2 sclk sread sdata sle 36 35 34 33 32 31 30 29 28 27 26 25 vdd vdd vdd tcxo vdd vdd vdd antenna connection to microcontroller tx/rx signal interface to microcontroller configuration interface t-stage lc filter matching loop filter external vco rf out v tune reference rset resistor r lna resistor chip enable to microcontroller notes 1. pins[13:18], pins[20:21], and pin 23 are test pins and are not used in normal operation. 08635-055 figure 56. typical application circuit (regulator capacitors and power supply decoupling not shown)
ADF7021-V rev. 0 | page 43 of 60 serial interface the serial interface allows the user to program the 16 32-bit registers using a 3-wire interface (sclk, sdata, and sle). it consists of a level shifter, 32-bit shift register, and 16 latches. signals should be cmos compatible. the serial interface is powered by the regulator and, therefore, is inactive when ce is low. data is clocked into the register, msb first, on the rising edge of each clock (sclk). data is transferred to one of 16 latches on the rising edge of sle. the destination latch is determined by the value of the four control bits (c4 to c1); these bits are the four lsbs, db3 to db0, as shown in figure 2 . data can also be read back on the sread pin. readback format the readback operation is initiated by writing a valid control word to the readback setup register and enabling the readback_ select bit (register 7, bit db8 = 1). the readback can begin after the control word has been latched with the sle signal. sle must be kept high while the data is being read out. each active edge at the sclk pin successively clocks the readback word out at the sread pin, msb first (see figure 57 ). the data appearing at the first clock cycle following the latch operation must be ignored. an extra clock cycle is needed after the 16 th readback bit to return the sread pin to tristate. therefore, 18 total clock cycles are needed for each readback. after the 18 th clock cycle, sle should be brought low. afc readback the afc readback is valid only during the reception of fsk signals with either the linear or correlator demodulator active. the afc readback value is formatted as a signed, 16-bit integer comprising bit rv16 to bit rv1 and is scaled according to the following formula: freq rb (hz) = ( afc readback demod clk )/2 18 in the absence of frequency errors, freq rb is equal to the if frequency of 100 khz. note that, for the afc readback to yield a valid result, the downconverted input signal must not fall outside the bandwidth of the analog if filter. at low input signal levels, the variation in the readback value can be improved by averaging. rssi readback the format of the rssi readback word is shown in figure 57 . it comprises the rssi-level information (bit rv7 to bit rv1), the current filter gain (fg2, fg1), and the current lna gain (lg2, lg1) setting. the filter and lna gain are coded in accordance with the definitions in the register 9agc register section. for signal levels below ?100 dbm, averaging the measured rssi values improves accuracy. the input power can be calculated from the rssi readback value as described in the rssi/agc section. readback with afc or linear demodulation on to perform any readback with the afc on, the agc must first be locked. to lock the agc, use the lock_threshold_mode bits (bits[db5:db4] in register 12) for packet reception. the lock threshold mode locks the threshold of the envelope detector, as well as the afc and agc circuits. it can be set to lock on recep- tion of a valid swd and remain locked until it is released by a subsequent spi command (lock_threshold_mode = 1). it can also be set to lock on reception of a valid swd for a specified number of bytes by setting lock_threshold_mode = 2; or it can be locked at any time by setting lock_threshold_ mode = 3. after the threshold is locked, a readback can be performed. the agc/afc lock is released by setting lock_threshold_mode = 0. battery voltage/adcin/temperature sensor readback the battery voltage is measured at pin vdd4. the readback information is contained in bit rv7 to bit rv1. this also applies to the readback of the voltage at the adcin pin and the temperature sensor. from the readback information, the battery or adcin voltage can be determined as follows: v battery = ( battery voltage readback )/21.1 v adcin = ( adcin voltage readback )/42.1 the temperature can be calculated as follows: temperature (c) = ?40 + [(68.4 ? temp readback) 9.32] readback mode afc readback db15 rv16 x x rv16 0 rssi readback battery voltage/adcin/ temp. sensor readback silicon revision filter cal readback readback value db14 rv15 x x rv15 0 db13 rv14 x x rv14 0 db12 rv13 x x rv13 0 db11 rv12 x x rv12 0 db10 rv11 lg2 x rv11 0 db9 rv10 lg1 x rv10 0 db8 rv9 fg2 x rv9 0 db7 rv8 fg1 x rv8 rv8 db6 rv7 rv7 rv7 rv7 rv7 db5 rv6 rv6 rv6 rv6 rv6 db4 rv5 rv5 rv5 rv5 rv5 db3 rv4 rv4 rv4 rv4 rv4 db2 rv3 rv3 rv3 rv3 rv3 db1 rv2 rv2 rv2 rv2 rv2 db0 rv1 rv1 rv1 rv1 rv1 08635-056 figure 57. readback value table
ADF7021-V rev. 0 | page 44 of 60 silicon revision readback the silicon revision readback word is valid without setting any other registers. the silicon revision word is coded with four quartets in bcd format. the product code (pc) is coded with three quartets extending from bit rv16 to bit rv5. the revision code (rc) is coded with one quartet extending from bit rv4 to bit rv1. the product code for the ADF7021-V should read back as pc = 0x212. the current revision code should read as rc = 0x0. filter bandwidth calibration readback the filter calibration readback word is contained in bit rv8 to bit rv1 (see figure 57 ). this readback can be used for manual filter adjustment, thereby avoiding the need to do an if filter calibration in some instances. the manual adjust value is programmed using register 5, bits[db19:db14]. to calculate the manual adjustment based on a filter calibration readback, use the following formula: if_filter_adjust = filter_cal_readback ? 128 the result should be programmed into register 5, bits[db19:db14] as described in the register 5if filter setup register section. interfacing to a microcontroller/dsp standard transmit/receive data interface the standard transmit/receive signal and configuration interface to a microcontroller is shown in figure 58 . in transmit mode, the ADF7021-V provides the data clock on the txrxclk pin, and the txrxdata pin is used as the data input. the transmit data is clocked into the ADF7021-V on the rising edge of txrxclk. miso aduc84x ADF7021-V mosi sclock ss p3.7 p3.2/int0 p2.4 p2.5 txrxdata txrxclk ce swd sread sle p2.6 p2.7 sdata sclk gpio 08635-057 figure 58. aduc84x to ADF7021-V connection diagram in receive mode, the ADF7021-V provides the synchronized data clock on the txrxclk pin. the received data is available on the txrxdata pin. the rising edge of txrxclk should be used to clock the receive data into the microcontroller. see figure 4 and figure 5 for the relevant timing diagrams. in 4fsk transmit mode, the msb of the transmit symbol is clocked into the ADF7021-V on the first rising edge of the data clock from the txrxclk pin. in 4fsk receive mode, the msb of the first payload symbol is clocked out on the first falling edge of the data clock after the swd and should be clocked into the microcontroller on the following rising edge. see figure 6 and figure 7 for the relevant timing diagrams. uart mode in uart mode, the txrxclk pin is configured to input trans- mit data in transmit mode. in receive mode, the receive data is available on the txrxdata pin, thus providing an asynchronous data interface. the uart mode can only be used with oversampled 2fsk modulation. figure 59 shows a possible interface to a micro- controller using the uart mode of the ADF7021-V. to enable the uart interface mode, set bit db28 in register 0 high. figure 8 and figure 9 show the relevant timing diagrams for uart mode. uart ADF7021-V txrxclk txrxdata txdata rxdata ce swd sread sle sdata sclk gpio microcontroller 08635-058 figure 59. ADF7021-V (uart mode) to asynchronous microcontroller interface spi mode in spi mode, the txrxclk pin is configured to input transmit data in transmit mode. in receive mode, the receive data is avail- able on the txrxdata pin. the data clock in both transmit and receive modes is available on the clkout pin. in transmit mode, data is clocked into the ADF7021-V on the rising edge of clkout. in receive mode, the txrxdata data pin should be sampled by the microcontroller on the rising edge of clkout. to enable spi interface mode, set bit db28 in register 0 high and set bits[db19:db17] in register 15 to 0x7. figure 8 and figure 9 show the relevant timing diagrams for spi mode; figure 60 shows the recommended interface to a micro- controller using the spi mode of the ADF7021-V. spi ADF7021-V txrxclk txrxdata miso mosi ce swd sread sle sdata sclk gpio microcontroller sclk clkout 08635-059 figure 60. ADF7021-V (spi mode) to microcontroller interface adsp-bf533 interface the suggested method of interfacing to the blackfin? adsp-bf533 is shown in figure 61 . mosi adsp-bf533 ADF7021-V miso pf5 rsclk1 dt1pri dr1pri rfs1 pf6 sdata sle txrxdata swd ce sck sclk sread txrxclk 08635-060 figure 61. adsp-bf533 to ADF7021-V connection diagram
ADF7021-V rev. 0 | page 45 of 60 register 0n register tr1 tx/rx 0 transmit receive 1 m3 m2 m1 muxout 0 regulator_ready (default) filter_cal_complete 0 0 digital_lock_detect 0 rssi_ready 1t x _ r x 1 logic_zero 1t r i s t a t e 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 logic_one u1 uart_mode 0disabled 1 enabled n8 n7 n6 n5 n4 n3 n2 n1 02 3 02 4 . . . 1 253 1 254 1 0 0 . . . 1 1 1 0 0 . . . . . . 1 1 1 1 1 1 1 1 . . . 0 1 1 1 1 . . . 1 0 1 1 1 . . . 1 0 0 1 1 . . . . . . 1 0 1 0 1 255 fractional_n integer_n tx/rx uart_mode muxout address bits n5 n4 n8 m5 m6 m7 m8 m12 m13 m15 n1 n2 n3 m14 m9 m10 m11 m4 m3 tr1 u1 m1 m3 m2 c2 (0) c1 (0) c3 (0) c4 (0) m1 m2 n7 n6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 fractional_n divide ratio 0 1 2 . . . 32,764 32,765 32,766 32,767 m15 0 0 0 . . . 1 1 1 1 m14 0 0 0 . . . 1 1 1 1 m13 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 08635-061 integer_n divide ratio f igure 62. register 0n register map ? the rf output frequency is calculated as follows: ? in the muxout map (bits[db31:db29]), filter_cal_ complete indicates when a coarse or coarse plus fine if filter calibration has finished. digital_lock_detect indicates when the pll has locked. rssi_ready indicates that the rssi signal has settled and an rssi readback can be performed. tx_rx gives the status of bit db27 in this register, which can be used to control an external tx/rx switch. for direct output, ? ? ? ? ? ? + = 15 2 _ _ n fractional n integer pfd rf out with rf_divide_by_2 (register 1, bit db18) enabled, ? ? ? ? ? ? + = 15 2 _ _ 5.0 n fractional n integer pfd rf out ? in uart/spi mode, the txrxclk pin is used to input the transmitted data. the received data is available on the txrxdata pin.
ADF7021-V rev. 0 | page 46 of 60 register 1oscillator register r3 r2 r1 0 0 . . . 1 1 2 . . . 7 1 0 . . . 1 0 1 . . . 1 x1 xosc_enable 0off 1on d1 xtal_ doubler 0 enabled 1 cp2 000.3 010.9 101.5 112.1 cl4 cl3 cl2 cl1 clkout_ divide ratio 0 off 0 0 . . . 1 0 1 0 . . . 1 2 4 . . . 0 0 1 . . . 1 0 0 0 . . . 1 30 cp_ current rf_divide_ by_2 xosc_ enable address bits xtal_ doubler xtal_ bias re5 re4 cl1 cl2 cl3 cl4 cp1 cp2 rfd1 re1 re2 re3 ve1 x1 xb1 xb2 d1 r3 c2 (0) c1 (1) c3 (0) c4 (0) r1 r2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 re6 db24 db1 db0 db2 db3 xb2 xb1 02 0 a 02 5 a 13 0 a 1 0 1 0 135a rfd1 rf_divide_by_2 0off on 1 ve1 0 1 db25 re7 r_counter clkout_ divide 08635-062 rf r_counter divide ratio reserved buffer_ impedance 50? high impedance xtal_bias disabled buffer_ impedance cp1 i cp (ma) rset = 3.6k ? f igure 63. register 1os cillator register map x the r_counter and xtal_doubler relationship is as follows: if xtal_doubler = 0, counter r xtal pfd _ if xtal_doubler = 1, counter r xtal pfd _ 2 u x clkout_divide is a divided-down and inverted version of the xtal and is available on pin 36 (clkout). x set xosc_enable high when using an external crystal. if using an external oscillator (such as tcxo) with cmos level outputs into pin osc2, set xosc_enable low. if using an external oscillator with a 0.8 v p-p clipped sine wave output into pin osc1, set xosc_enable high.
ADF7021-V rev. 0 | page 47 of 60 register 2transmit modulation register p6 0 0 0 0 . . 1 ... ... ... ... ... ... ... ... p5 0 0 0 0 . . 1 p2 0 0 1 1 . . 1 p1 0 1 0 1 . . 1 0 (pa off) 1 (?16.0dbm) 2 3 . . 63 (+13dbm) tfd9 0 0 0 0 . 1 tfd3 0 0 0 0 . 1 ... ... ... ... ... ... ... tfd2 0 0 1 1 . 1 tfd1 0 1 0 1 . 1 0 1 2 3 . 511 tx_frequency_deviation power_amplifier txdata_ invert pa_bias pa_ramp modulation_ scheme address bits pa_ enable pe1 0 1 pa_enable off on pa2 0 0 1 1 pa1 0 1 0 1 pa_bias 5a 7a 9a 11 a di2 0 0 1 1 di1 0 1 0 1 txdata_invert normal invert clk invert data inv clk and data s3 0 0 0 0 1 1 1 1 s2 0 0 1 1 0 0 1 1 modulation_scheme 2fsk gaussian 2fsk 3fsk 4fsk oversampled 2fsk raised cosine 2fsk raised cosine 3fsk raised cosine 4fsk s1 0 1 0 1 0 1 0 1 pr3 0 0 0 0 1 1 1 1 pr2 0 0 1 1 0 0 1 1 no ramp 256 codes/bit 128 codes/bit 64 codes/bit 32 codes/bit 16 codes/bit 8 codes/bit 4 codes/bit pr1 pa_ramp rate 0 1 0 1 0 1 0 1 tfd5 tfd4 tfd8 pr1 pr2 pr3 pa1 p3 p4 p6 tfd1 tfd2 tfd3 p5 pa2 p1 p2 pe1 s3 tfd9 di1 di2 c2 (1) c1 (0) c3 (0) c4 (0) s1 s2 tfd7 tfd6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 r-cosine_ alpha db30 nrc1 nrc1 0 1 r-cosine_alpha 0.7 0.5 (default) f dev power_ amplifier 08635-063 f igure 64. register 2transmit modulation register map ? the 2fsk/3fsk/4fsk frequency deviation is expressed as follows: for direct rf output, frequency deviation (hz) = 16 2 pfdon cy_deviati tx_frequen with rf_divide_by_2 (register 1, bit db18) enabled, frequency deviation (hz) = 16 2 5.0 pfdon cy_deviati tx_frequen w here: tx_frequency_deviation is set by bits[db27:db19]. pfd is the pfd frequency. ? in the case of 4fsk, there are tones at 3 the frequency deviation and at 1 the frequency deviation. ? the power amplifier (pa) ramps at the programmed rate (bits[db10:db8]) until it reaches its programmed level (bits[db18:db13]). if the pa is enabled/disabled by the pa_enable bit (bit db7), it ramps up and down. if it is enabled/disabled by the tx/rx bit (register 0, bit db27), it ramps up and turns hard off. ? r-cosine_alpha sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. the alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7.
ADF7021-V rev. 0 | page 48 of 60 register 3transmit/receive clock register fs8 0 0 . 1 1 fs7 0 0 . 1 1 fs3 0 0 . 1 1 ... ... ... ... ... ... fs2 0 1 . 1 1 fs1 1 0 . 0 1 cdr_clk_ divide 1 2 . 254 255 bk2 0 0 1 1 bk1 0 1 0 1 bbos_clk_divide 4 8 16 32 sk8 0 0 . 1 1 sk7 0 0 . 1 1 sk3 0 0 . 1 1 ... ... ... ... ... ... sk2 0 1 . 1 1 sk1 1 0 . 0 1 seq_clk_divide 1 2 . 254 255 ok2 0 0 ... 1 ok1 0 1 ... 1 demod_clk_divide invalid 1 ... 15 seq_clk_divide agc_clk_divide cdr_clk_divide bbos_clk_ divide demod_clk_ divide address bits gd6 0 0 ... 1 gd5 0 0 ... 1 gd3 0 0 ... 1 gd4 0 0 ... 1 gd2 0 0 ... 1 gd1 0 1 ... 1 agc_clk_divide invalid 1 ... 63 sk8 sk7 fs1 fs2 fs3 fs4 fs8 sk1 sk3 sk4 sk5 sk6 sk2 fs5 fs6 fs7 ok2 ok1 ok4 ok3 c2 (1) c1 (1) c3 (0) c4 (0) bk1 bk2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 gd6 gd5 gd1 gd2 gd3 gd4 db24 db25 db28 db27 db26 db29 db30 db31 db1 db0 db2 db3 ok3 0 0 ... 1 0 0 ... 1 ok4 08635-064 f igure 65. register 3transmit/receive clock register map ? baseband offset clock frequency (bbos clk) must be greater than 1 mhz and less than 2 mhz, where b bos clk = ( xtal / bbos_clk_divide ) ? set the demodulator clock (demod clk) such that 2 mhz demod clk 15 mhz, where d emod clk = ( xtal / demod_clk_divide ) ? for 2fsk/3fsk, the clock/data recovery frequency (cdr clk) must be within 2% of (32 data rate). for 4fsk, the cdr clk must be within 2% of (32 symbol rate). cdr clk = ( demod clk / cdr_clk_divide ) ? the sequencer clock (seq clk) supplies the clock to the digital receive block. it should be as close to 100 khz as possible. seq clk = ( xtal/ seq_clk_divide ) ? the time allowed for each agc step to settle is determined by the agc update rate. it should be set close to 3 khz. agc update rate (hz) = ( seq clk/agc_clk_divide )
ADF7021-V rev. 0 | page 49 of 60 register 4demodulator setup register discriminator_bw dot_product post_demod_bw rx_ invert if_filter_bw address bits td4 td3 ri1 ri2 dw1 dw2 dw6 dw7 dw9 dw10 td1 td2 dw8 dw3 dw4 dw5 dp1 ds3 c2 (0) c1 (0) c3 (1) c4 (0) ds1 ds2 td6 td5 td10 td9 td7 td8 ifb2 ifb1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ds1 0 1 0 1 0 1 0 1 demod_scheme 2fsk linear demodulator 2fsk correlator demodulator 3fsk demodulator 4fsk demodulator reserved reserved reserved reserved dp1 0 1 dot_product cross_product dot_product ri1 0 1 0 1 rx_invert normal invert clk invert data invert clk/data ifb1 0 1 0 1 if_filter _ bw ds2 ds3 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 ri2 ifb2 0 0 1 1 dw3 0 0 . . . . 1 dw1 1 0 . . . . 1 post_demod_bw 1 2 . . . . 1023 dw2 0 1 . . . . 1 dw10 0 0 . . . . 1 dw6 0 0 . . . . 1 . . . . . . . . dw5 0 0 . . . . 1 dw4 0 0 . . . . 1 td3 0 0 . . . . 1 td1 1 0 . . . . 0 discriminator_bw 1 2 . . . . 660 td2 0 1 . . . . 0 td10 0 0 . . . . 1 td6 0 0 . . . . 0 . . . . . . . . td5 0 0 . . . . 1 td4 0 0 . . . . 0 demod_ scheme 0 8635-065 9khz 13.5khz 18.5khz invalid f igure 66. register 4demodulator setup register map ? to solve for discriminator_bw, (bits[db19:db10]), use the following equation: ? ? ? ? ? ? ? ? = 3 10400 _ k clk demod bwtor discrimina where the maximum value = 660. for 2fsk, ? ? ? ? ? ? ? ? = 3 10100 for 3fsk, ? ? ? ? ? ? ? ? = 2 10100 3 for 4fsk, ? ? ? ? ? ? ? ? = 4 10100 3 4 where: round is rounded to the nearest integer. round 4fsk is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. f dev is the transmit frequency deviation in hz. for 4fsk, f dev is the frequency deviation used for the 1 symbols (that is, the inner frequency deviations). ? rx_invert (bits[db9:db8]) and dot_product (bit db7) must be set as indicated in table 16 and table 17 . ? post_demod_bw (bits[db29:db20]) sets the bandwidth of the postdemodulator filter. to solve for post_demod_bw, use the following equation: clk demod f _bw post_demod cutoff = 2 11 where f cutoff (the cutoff frequency of the postdemodulator filter) should typically be set equal to 0.75 the data rate in 2fsk. in 3fsk, it should be set equal to the data rate, whereas in 4fsk, it should be set equal to 1.6 the symbol rate.
ADF7021-V rev. 0 | page 50 of 60 register 5if filter setup register ir_phase_ adjust_mag ir_phase_ adjust_direction ir_gain_ adjust_i/q ir_gain_ adjust_up/dn ir_gain_ adjust_mag if_filter_divider if_cal_coarse if_filter_adjust address bits ifa1 ifd9 ifd5 ifd6 pm2 pm3 gm1 gm2 gm4 gm5 ifd7 ifd8 gm3 pm4 pd1 ifd4 ifd3 c2 (0) c1 (1) c3 (1) c4 (0) ifd1 cc1 ifd2 ifa3 ifa2 pm1 ifa6 ifa4 ifa5 ga1 gq1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 cc1 if_cal_coarse 0 1 disabled enabled pd1 0 1 ir_phase_adjust_direction adjust i ch adjust q ch ga1 0 1 ir_gain_adjust_up/dn gain attenuate gq1 0 1 ir_gain_adjust_i/q adjust i ch adjust q ch ifd3 0 0 . . . . 1 ifd1 if_filter_ divider 1 0 . . . . 1 1 2 . . . . 511 ifd2 0 1 . . . . 1 ifa2 0 0 1 .. 1 0 0 1 . 1 ifa6 0 0 0 .. 0 1 1 1 1 1 gm3 ir_gain_ adjust_mag gm5 0 0 0 . 1 ifd9 0 0 . . . . 1 ifd6 0 0 . . . . 1 . . . . . . . . ifd5 0 0 . . . . 1 ifd4 0 0 . . . . 1 0 1 0 .. 1 0 1 0 . 1 ifa1 if_filter_adjust ... ... ... ... ... ... ... ... ... ... ... 0 +1 +2 ... +31 0 ?1 ?2 ... ?31 gm4 gm2 gm1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 31 pm3 ir_phase_ adjust_mag pm4 pm2 pm1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 15 ifa5 0 0 0 .. 1 0 0 0 . 1 08635-066 f igure 67. register 5if filter setup register map ? a coarse if filter calibration is performed when the if_cal_coarse bit (bit db4) is set. if the if_fine_ cal bit (register 6, bit db4) has been previously set, a fine if filter calibration is automatically performed after the coarse calibration. ? set if_filter_divider such that khz50 __ = ? if_filter_adjust allows the if fine filter calibration result to be programmed directly on subsequent receiver power-ups, thereby eliminating the need to redo a fine filter calibration in some instances. see the filter bandwidth calibration readback section for information about using the if_filter_adjust bits. ? bits[db31:db20] are used for image rejection calibration. see the image rejection calibration section for information about how to program these parameters.
ADF7021-V rev. 0 | page 51 of 60 register 6if fine calibration setup register if_cal_lower_tone_divide if_cal_upper_tone_divide if_cal_dwell_time if_fine_ cal address bits cd3 cd2 cd6 lt4 lt5 lt6 lt7 ut3 ut4 ut6 ut7 ut8 cd1 ut5 lt8 ut1 ut2 lt3 lt2 cd7 c2 (1) c1 (0) c3 (1) c4 (0) fc1 lt1 cd5 cd4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db25 db1 db0 db2 db3 fc1 0 1 if_fine_cal disabled enabled ut3 0 0 0 . . 1 ut1 1 0 1 . . 1 if_cal_upper_ tone_divide 1 2 3 . . ut2 0 1 1 . . 1 ut8 0 0 0 . . 0 ... ... ... ... ... ... ... 127 lt3 0 0 0 . . 1 lt1 1 0 1 . . 1 1 2 3 . . lt2 0 1 1 . . 1 lt8 0 0 0 . . 1 ... ... ... ... ... ... ... 255 if_cal_lower_ tone_divide cd3 0 0 0 . . 1 cd1 1 0 1 . . 1 if_cal_ dwell_time 1 2 3 . . cd2 0 1 1 . . 1 cd7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 db28 irc1 db29 db30 irc2 ird1 ir_cal_ source_ drive_level ir_cal_ source 2 irc1 0 1 0 1 ir_cal_source_ drive_level irc2 0 0 1 1 off low med high ird1 0 1 ir_cal_source 2 source 2 off source 2 on 0 0 0 . . 1 lt7 0 0 0 . . 1 ut7 08635-067 f igure 68. register 6if fine calibration setup register map ? a fine if filter calibration is set by enabling the if_fine_ cal bit (bit db4). a fine calibration is performed only when register 5 is written to and register 5, bit db4 is set. ? lower tone frequency (khz) = 2 upper tone frequency (khz) = 2 it is recommended that the lower tone and the upper tone be set as shown in table 24 . table 24. if filter fine calibration tone frequencies if filter bandwidth (khz) lower tone frequency (khz) upper tone frequency (khz) 9 78.1 116.3 13.5 79.4 116.3 18.5 78.1 119 ? the if tone calibration time is the amount of time that is spent at an if calibration tone. it is dependent on the sequencer clock. it is recommended that the if tone calibration time be at least 800 s. clkseq ll_time if_cal_dwe timencalibratio toneif = the total time for a fine if filter calibration is i f tone calibration time 10 ? bits[db30:db28] control the internal source for the image rejection (ir) calibration. the ir_cal_source_drive_ level bits (bits[db29:db28]) set the drive strength of the source, whereas the ir_cal_source 2 bit (bit db30) allows the frequency of the internal signal source to be divided by 2.
ADF7021-V rev. 0 | page 52 of 60 register 7readback setup register ad1 ad2 rb1 rb2 rb3 db8 db7 db6 db5 db4 db3 db2 c2 (1) c1 (1) control bits db1 db0 c3 (1) c4 (0) readback_ select adc_ mode ad2 0 0 1 1 ad1 0 1 0 1 adc_mode measure rssi battery voltage temp sensor to external pin rb2 0 0 1 1 rb1 0 1 0 1 readback mode afc word adc output filter cal silicon rev rb3 0 1 readback_select disabled enabled 0 8635-068 f igure 69. register 7readback setup register map ? readback of the measured rssi value is valid only in rx mode. readback of the battery voltage, temperature sensor, or voltage at the external adcin pin is not valid in rx mode. ? to read back the battery voltage, the temperature sensor, or the voltage at the external adcin pin in tx mode, the user should first power up the adc using register 8, bit db8 because it is turned off by default in tx mode to save power. ? for afc readback, use the following equations (see the readback format section): freq rb (hz) = ( afc readback demod clk )/2 18 v battery = battery voltage readback /21.1 v adcin = adcin voltage readback /42.1 temperature (c) = ?40 + [(68.4 ? temp readback ) 9.32]
ADF7021-V rev. 0 | page 53 of 60 register 8power-down test register pd1 pd3 res pd4 pd5 db8 db7 db6 db5 db4 db3 db2 c2 (0) c1 (0) control bits db1 db0 c3 (0) c4 (1) log_amp_ enable synth_ enable reserved lna/mixer_ enable filter_ enable adc_ enable demod_ enable tx/rx_switch_ enable pa_enable_ rx_mode counter_ reset rx_reset cr1 rr2 rr1 db15 db14 db13 db12 db11 le1 pd6 db10 db9 sw1 pd7 pd7 0 1 pa_enable_rx_mode pa off pa on cr1 0 1 counter_reset normal reset sw1 0 1 tx/rx_switch_enable default (on) off pd6 0 1 demod_enable demod off demod on pd5 0 1 adc_enable adc off adc on rr2 0 1 cdr_reset normal reset rr1 0 1 demod_reset normal reset le1 0 1 log_amp_enable log amp off log amp on pd4 0 1 filter_enable filter off filter on pd3 0 1 lna/mixer_enable lna/mixer off lna/mixer on pd1 0 1 synth_enable synth off synth on 08635-069 figure 70. register 8power-down test register map it is not necessary to write to this register under normal operating conditions. for a combined lna/pa matching network, bit db11 should always be set to 0, which enables the internal tx/rx switch. this is the power-up default condition.
ADF7021-V rev. 0 | page 54 of 60 register 9agc register agc_high_threshold lna_ gain agc_ mode filter_ gain lna_ bias filter_ current mixer_ linearity lna_mode agc_low_threshold address bits fg2 fg1 gl5 gl6 gl7 gh1 gh5 gh6 gm1 gm2 lg1 lg2 gh7 gh2 gh3 gh4 gl4 gl3 c2 (0) c1 (1) c3 (0) c4 (1) gl1 gl2 fi1 lm1 ml1 li1 li2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 fi1 0 1 filter_current low high agc_mode gm2 0 0 1 1 0 1 0 1 gm1 auto agc manual agc freeze agc reserved fg2 0 0 1 1 fg1 filter_gain 0 1 0 1 8 24 72 invalid lg2 0 0 1 1 lg1 0 1 0 1 lna_gain 3 10 30 invalid gl3 0 0 0 1 . . . 1 1 1 gl1 1 0 1 0 . . . 1 0 1 agc_low_ threshold 1 2 3 4 . . . 61 62 63 gl2 0 1 1 0 . . . 0 1 1 gl7 0 0 0 0 . . . 1 1 1 gl6 0 0 0 0 . . . 1 1 1 gl5 0 0 0 0 . . . 1 1 1 gl4 0 0 0 0 . . . 1 1 1 gh3 0 0 0 1 . . . 1 1 0 gh1 1 0 1 0 . . . 0 1 0 agc_high_ threshold 1 2 3 4 . . . 78 79 80 gh2 0 1 1 0 . . . 1 1 0 gh7 0 0 0 0 . . . 1 1 1 gh6 0 0 0 0 . . . 0 0 0 gh5 0 0 0 0 . . . 0 0 1 gh4 0 0 0 0 . . . 1 1 0 li2 0 li1 0 lna_bias 800a (default) lm1 0 1 lna_mode default reduced gain ml1 0 1 mixer_linearity default high 08635-070 f igure 71. register 9agc register map ? it is necessary to program this register only if agc settings other than the defaults are required. ? in receive mode, agc is set to automatic agc by default on power-up. the default thresholds are agc_low_ threshold = 30 and agc_high_threshold = 70. see the rssi/agc section for details. ? agc high and low threshold values must be more than 30 apart to ensure correct operation. ? an lna gain of 30 is available only if lna_mode (bit db25) is set to 0.
ADF7021-V rev. 0 | page 55 of 60 register 10afc register ki kp afc_scaling_factor max_afc_range afc_en address bits kp3 kp2 ma3 m4 m5 m6 m7 m11 m12 ki2 ki3 ki4 kp1 ki1 m8 m9 m10 m3 m2 ma4 ma5 c2 (1) c1 (0) c3 (0) c4 (1) ae1 m1 ma2 ma6 ma7 ma8 ma1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 kp1 0 1 . 1 2^0 2^1 ... 2^7 ae1 0 1 afc_en afc off afc on ma3 0 0 0 1 . . . 1 1 1 ma1 1 0 1 0 . . . 1 0 1 max_afc_range 1 2 3 4 . . . 253 254 255 ma2 0 1 1 0 . . . 0 1 1 ma8 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... ... 0 0 . 1 0 0 . 1 kp2 kp3 kp ki1 0 1 . 1 2^0 2^1 ... 2^15 0 0 . 1 0 0 . 1 ki2 k i3 ki ki4 0 0 . 1 m3 0 0 0 1 . . . 1 1 1 m1 1 0 1 0 . . . 1 0 1 afc_scaling_ factor 1 2 3 4 . . . 4093 4094 4095 m2 0 1 1 0 . . . 0 1 1 m12 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... ... 08635-071 f igure 72. register 10afc register map ? the afc_scaling_factor can be expressed as ? ? ? ? ? ? ? ? = 5002 _ _ 24 ? the settings for ki and kp affect the afc settling time and afc accuracy. the allowable range for each parameter is ki > 6 and kp < 7. ? the recommended settings for optimal afc performance are ki = 11 and kp = 4. to trade off between afc settling time and afc accuracy, the ki and kp parameters can be adjusted from the recommended settings (staying within the allowable range) such that a fc correction range = max_afc_range 500 hz ? when rf_divide_by_2 (register 1, bit db18) is enabled, the programmed afc correction range is halved. the user must account for this halving by doubling the programmed max_afc_range value. ? signals that are within the afc pull-in range but outside the if filter bandwidth are attenuated by the if filter. as a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the afc.
ADF7021-V rev. 0 | page 56 of 60 register 11sync word detect register pl2 0 0 1 1 pl1 0 1 0 1 sync_byte_ length 12 bits 16 bits 20 bits 24 bits mt2 0 0 1 1 mt1 0 1 0 1 matching_ tolerance accept 0 errors accept 1 error accept 2 errors accept 3 errors sync_byte_sequence control bits sync_byte_ length matching_ tolerance mt2 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sb11 sb12 sb13 sb14 sb15 sb16 sb17 sb18 sb19 sb20 sb21 sb22 sb23 sb24 mt1 c2 (1) c1 (1) c3 (0) c4 (1) pl1 pl2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 08635-072 figure 73. register 11sync word detect register map register 12swd/threshold setup register data_packet_length control bits lock_ threshold_ mode swd_mode il2 il1 c2 (0) c1 (0) c3 (1) c4 (1) lm1 lm2 db15 db14 db13 db12 db11 db10 db9 db8 dp8 dp7 dp6 dp5 dp4 dp3 dp2 dp1 db7 db6 db5 db4 db1 db0 db2 db3 lmx lock_threshold_mode 0 threshold free running 1 lock threshold after next sync word 2 lock threshold after next sync word for data packet length number of bytes 3 lock threshold dpx data_packet_length 0 invalid 1 1 byte ... ... 255 255 bytes ilx swd_mode 0 swd pin low 1 swd pin high after next sync word 2 swd pin high after next sync word for data packet length number of bytes 3 swd pin high 0 8635-073 figure 74. register 12swd/threshold setup register map lock threshold locks the threshold of the envelope detector. this has the effect of locking the slicer in linear demodulation and locking the afc and agc loops when using linear or correlator demodulation.
ADF7021-V rev. 0 | page 57 of 60 register 133fsk/4fsk demodulation register see the receiver setup section for information about programming these settings. 3fsk_cdr_threshold viterbi_ path_ memory 3fsk/4fsk_ slicer_threshold control bits 3fsk_viterbi_ detector phase_ correction st4 st5 st6 st7 vd1 pc1 vm1 vm2 vt1 vt2 vt3 vt4 vt5 vt6 vt7 st3 c2 (0) c1 (1) c3 (1) c4 (1) st1 st2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db1 db0 db2 db3 3fsk_preamble_ time_validate ptv1 ptv2 ptv3 ptv4 db24 db23 db22 db25 4 bits 0 0 1 1 vm2 viterbi_path _ memory vm1 0 1 0 1 6 bits 8 bits 32 bits phase_ correction 0 disabled 1 enabled pc1 3fsk_viterbi_ detector 0 disabled 1 enabled vd1 st3 0 0 0 . . 1 st1 1 0 1 . . 1 3fsk/4fsk_slicer_ threshold 1 2 3 . . st2 0 1 1 . . 1 st7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 00 0... 0 off vt3 0 0 0 . . 1 vt1 1 0 1 . . 1 3fsk_cdr_ threshold 1 2 3 . . vt2 0 1 1 . . 1 vt7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 00 0... 0 off ptv3 0 0 0 . . 1 ptv1 1 0 1 . . 1 3fsk_premable_ time_validate 1 2 3 . . ptv2 0 1 1 . . 1 ptv4 0 0 0 . . 1 15 00 0 0 0 08635-074 figure 75. register 133fsk/4f sk demodulation register map
ADF7021-V rev. 0 | page 58 of 60 register 14test dac register test_dac_gain test_dac_offset test_ tdac_en ed_peak_ response ed_leak_ factor pulse_ extension address bits tg3 tg2 er2 to4 to5 to6 to7 to11 to12 to14 to15 to16 tg1 to13 to8 to9 to10 to3 to2 ef1 ef2 c2 (1) c1 (0) c3 (1) c4 (1) te1 to1 er1 ef3 pe1 pe2 tg4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 pex ed_peak_response 0 1 2 3 full response to peak 0.5 response to peak 0.25 response to peak 0.125 response to peak tgx test_dac_gain 0 1 ... 15 no gain 2^1 ... 2^15 test_tdac_en test dac disabled test dac enabled te1 0 1 efx ed_leak_factor 0 1 2 3 4 5 6 7 leakage = 2^?8 2^?9 2^?10 2^?11 2^?12 2^?13 2^?14 2^?15 08635-075 erx pulse_extension 0 1 2 3 no pulse extension extended by 1 extended by 2 extended by 3 figure 76. register 14test dac register map whereas the correlators and filters are clocked by demod clk, the test dac is clocked by cdr clk. note that although the test dac functions in regular user mode, the best performance is achieved when cdr clk is increased to or above the frequency of demod clk. the cdr block does not function when this condition exists. the demodulator tuning parameters, pulse_extension, ed_leak_factor, and ed_peak_response, can be enabled only by setting register 15, bits[db7:db4] to 0x9. using the on-chip test dac the on-chip test dac can be used to implement analog demodulation or to provide access for measurement of fsk demodulator output snr or cnr. for detailed information about using the test dac, see the an-852 application note. programming register 14 enables the test dac. both the linear and correlator demodulator outputs can be multiplexed into the dac. t he test dac allows the postdemodulator filter output for both linear and correlator demodulators to be viewed externally. the test dac also takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order, error feedback - converter. the output can be viewed on the swd pin. this signal, when filtered appropriately, can then be used to do the following: register 14 allows a fixed offset term to be removed from the signal (to remove the if component in the linear demodulator case). it also has a signal gain term to allow the usage of the maximum dynamic range of the dac. ? monitor the signals at the fsk postdemodulator filter output. this allows the demodulator output snr to be measured. eye diagrams of the received bit stream can also be constructed to measure the received signal quality. ? provide analog fm demodulation.
ADF7021-V rev. 0 | page 59 of 60 register 15test mode register rx_test_ modes tx_test_ modes - _test_ modes pfd/cp_ test_modes pll_test_ modes analog_test_ modes clk_mux force_ld_ high reg1_pd cal_ override address bits pm4 pm3 am3 tm1 tm2 tm3 sd1 pc2 pc3 cm2 cm3 pm1 pm2 cm1 sd2 sd3 pc1 rt4 rt3 am4 fh1 rd1 co2 co1 c2 (1) c1 (1) c3 (1) c4 (1) rt1 rt2 am2 am1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 analog_test_modes 0 amx band gap voltage 1 40a current from reg4 2 filter i channel: stage 1 3 filter i channel: stage 2 4 filter i channel: stage 1 5 filter q channel: stage 1 6 filter q channel: stage 2 7 filter q channel: stage 1 8 adc reference voltage 9 bias current from rssi 5a 10 filter coarse cal oscillator output 11 analog rssi i channe l 12 13 14 15 bias current from bb filter tx_test_modes 0 tmx tx carrier only 1 tx + f dev tone only 2 tx ? f dev tone only 3 tx "1010" pattern 4 tx pn9 data sequence 5 tx swd pattern repeatedly 6 - _test_modes 0 sdx default, 3rd-order - , no dither 1 1st-order - 2 2nd-order - 3 dither to first stage 4 dither to second stage 5 ditherto third stage 6 dither 8 7 dither 32 0 pmx normal operation pll_test_modes 1r div 2n div 3 rcntr/2 on muxout 4 ncntr/2 on muxout 5 acntr to muxout 6 pfd pump up to muxout 7 pfd pump dnto muxout 8 s data to muxout (or sread) 9 analog lock detect on muxout 10 end of coarse cal on muxout 11 end of fine cal on muxout 12 13 test mux selects data 14 lock detect precision 15 reserved pfd/cp_test_modes 0 pcx default, no bleed 1 (+ve) constant bleed 2 (?ve) constant bleed 3 (?ve) pulsed bleed 4 (?ve) pulse bld, delay up 5 cp pump up 6 cp tristate 7 cp pump dn clk_mux on clkout pin 0 cmx 1 2 3 4 5 6 7 cal_override 0 cox auto cal 1 override gain 2 override bw 3 override bw and gain force_ld_high 0 fh1 normal 1force reg1_pd 0 rd1 normal 1power-down force new prescaler config for all n normal operation normal, no output demod clk cdr clk seq clk bb offset clk - clk adc clk txrxclk rx_test_modes 0 rtx normal 1 sclk, sdata i,q 2 reverse i,q 3 linear slicer on txrxdata 4 correlator slicer on txrxdata additional filtering on i,q envelope detector watchdog disabled reserved enable reg 14 demod parameters prohibit cal active enable demod during cal force cal active 5 6 i,q to txrxclk, txrxdata 7 8 9 10 11 12 power down ddt and ed in t/4 mode 13 14 15 sdata to cdr 3fsk slicer on txrxdata 08635-076 offset loop +ve fback v (i ch) summed output of rssi rectifier+ summed output of rssi rectifier? f igure 77. register 15test mode register map x analog rssi can be viewed on the test_a pin by setting analog_test_modes (bits[db27:db24]) to 11. x tx_test_modes can be used to enable modulation test. x the cdr block can be bypassed by setting rx_test_ modes to 4, 5, or 6, depending on the demodulator used.
ADF7021-V rev. 0 | page 60 of 60 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 4.25 4.10 sq 3.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 042809-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 78. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADF7021-Vbcpz ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 ADF7021-Vbcpz-rl ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 eval-adf70xxmbz2 evaluation platform mother board eval-ADF7021-Vdb1z 450 mhz to 470 mhz daughter board eval-ADF7021-Vdb2z 868 mhz to 870 mhz daughter board 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08635-0-4/10(0)

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